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/linux/Documentation/devicetree/bindings/timer/
H A Dnuvoton,npcm7xx-timer.yaml25 - description: The timer interrupt of timer 0
29 - description: The reference clock for timer 0
52 reg = <0xf0008000 0x50>;
/linux/Documentation/devicetree/bindings/media/
H A Datmel,isc.yaml41 const: 0
64 enum: [0, 1]
68 enum: [0, 1]
72 enum: [0, 1]
97 reg = <0xf0008000 0x4000>;
101 #clock-cells = <0>;
108 vsync-active = <0>;
/linux/arch/arm/probes/
H A Ddecode-thumb.c20 DECODE_REJECT (0xfe4f0000, 0xe80f0000),
24 DECODE_REJECT (0xffc00000, 0xe8000000),
27 DECODE_REJECT (0xffc00000, 0xe9800000),
30 DECODE_REJECT (0xfe508000, 0xe8008000),
32 DECODE_REJECT (0xfe50c000, 0xe810c000),
34 DECODE_REJECT (0xfe402000, 0xe8002000),
40 DECODE_CUSTOM (0xfe400000, 0xe8000000, PROBES_T32_LDMSTM),
50 DECODE_OR (0xff600000, 0xe8600000),
53 DECODE_EMULATEX (0xff400000, 0xe9400000, PROBES_T32_LDRDSTRD,
54 REGS(NOPCWB, NOSPPC, NOSPPC, 0, 0)),
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dat91sam9n12.dtsi42 #size-cells = <0>;
44 cpu@0 {
47 reg = <0>;
53 reg = <0x20000000 0x10000000>;
59 #clock-cells = <0>;
60 clock-frequency = <0>;
65 #clock-cells = <0>;
66 clock-frequency = <0>;
72 reg = <0x00300000 0x8000>;
75 ranges = <0 0x00300000 0x8000>;
[all …]
H A Dat91sam9x5.dtsi44 #size-cells = <0>;
46 cpu@0 {
49 reg = <0>;
55 reg = <0x20000000 0x10000000>;
61 #clock-cells = <0>;
62 clock-frequency = <0>;
67 #clock-cells = <0>;
68 clock-frequency = <0>;
73 #clock-cells = <0>;
80 reg = <0x00300000 0x8000>;
[all …]
H A Dsama5d3.dtsi46 #size-cells = <0>;
47 cpu@0 {
50 reg = <0x0>;
51 d-cache-size = <0x8000>; // L1, 32 KB
52 i-cache-size = <0x8000>; // L1, 32 KB
58 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>;
63 reg = <0x20000000 0x8000000>;
69 #clock-cells = <0>;
70 clock-frequency = <0>;
75 #clock-cells = <0>;
[all …]
H A Dsama5d2.dtsi29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
35 d-cache-size = <0x8000>; // L1, 32 KB
36 i-cache-size = <0x8000>; // L1, 32 KB
43 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>;
48 reg = <0x740000 0x1000>;
64 reg = <0x73c000 0x1000>;
80 reg = <0x20000000 0x20000000>;
86 #clock-cells = <0>;
[all …]
H A Dsam9x60.dtsi37 #size-cells = <0>;
39 cpu@0 {
42 reg = <0>;
48 reg = <0x20000000 0x10000000>;
54 #clock-cells = <0>;
59 #clock-cells = <0>;
65 reg = <0x00300000 0x100000>;
68 ranges = <0 0x00300000 0x100000>;
79 #size-cells = <0>;
81 reg = <0x00500000 0x100000
[all …]
H A Dsama5d4.dtsi47 #size-cells = <0>;
49 cpu@0 {
52 reg = <0>;
53 d-cache-size = <0x8000>; // L1, 32 KB
54 i-cache-size = <0x8000>; // L1, 32 KB
61 reg = <0x20000000 0x20000000>;
67 #clock-cells = <0>;
68 clock-frequency = <0>;
73 #clock-cells = <0>;
74 clock-frequency = <0>;
[all …]