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/freebsd/sys/contrib/device-tree/Bindings/mips/lantiq/
H A Dfpi-bus.txt20 ranges = <0x0 0x10000000 0xf000000>;
21 reg = <0x1f400000 0x1000>,
22 <0x10000000 0xf000000>;
24 lantiq,offset-endianness = <0x4c>;
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dqcom,qdu1000-tlmm.yaml61 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|150)$"
106 reg = <0xf000000 0x1000000>;
112 gpio-ranges = <&tlmm 0 0 151>;
H A Dqcom,sa8775p-tlmm.yaml60 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[0-7])$"
112 reg = <0xf000000 0x1000000>;
118 gpio-ranges = <&tlmm 0 0 14
[all...]
H A Dqcom,sc7280-pinctrl.yaml58 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-6][0-9]|17[0-4])$"
115 reg = <0xf000000 0x1000000>;
121 gpio-ranges = <&tlmm 0 0 17
[all...]
/freebsd/lib/msun/src/
H A De_hypotf.c26 ha &= 0x7fffffff; in hypotf()
28 hb &= 0x7fffffff; in hypotf()
32 if((ha-hb)>0xf000000) {return a+b;} /* x/y > 2**30 */ in hypotf()
33 k=0; in hypotf()
34 if(ha > 0x58800000) { /* a>2**50 */ in hypotf()
35 if(ha >= 0x7f800000) { /* Inf or NaN */ in hypotf()
37 w = fabsl(x+0.0L)-fabsf(y+0); in hypotf()
38 if(ha == 0x7f800000) w = a; in hypotf()
39 if(hb == 0x7f800000) w = b; in hypotf()
43 ha -= 0x22000000; hb -= 0x22000000; k += 68; in hypotf()
[all …]
/freebsd/sys/contrib/ena-com/ena_defs/
H A Dena_regs_defs.h38 ENA_REGS_RESET_NORMAL = 0,
63 /* 0 base */
64 #define ENA_REGS_VERSION_OFF 0x0
65 #define ENA_REGS_CONTROLLER_VERSION_OFF 0x4
66 #define ENA_REGS_CAPS_OFF 0x8
67 #define ENA_REGS_CAPS_EXT_OFF 0xc
68 #define ENA_REGS_AQ_BASE_LO_OFF 0x10
69 #define ENA_REGS_AQ_BASE_HI_OFF 0x14
70 #define ENA_REGS_AQ_CAPS_OFF 0x18
71 #define ENA_REGS_ACQ_BASE_LO_OFF 0x20
[all …]
/freebsd/sys/contrib/device-tree/src/mips/brcm/
H A Dbcm7125.dtsi9 #size-cells = <0>;
13 cpu@0 {
16 reg = <0>;
31 #address-cells = <0>;
41 #clock-cells = <0>;
47 #clock-cells = <0>;
57 ranges = <0 0x10000000 0x01000000>;
61 reg = <0x441400 0x30>, <0x441600 0x30>;
72 reg = <0x401800 0x30>;
81 reg = <0x400000 0xdc>;
[all …]
H A Dbcm7346.dtsi9 #size-cells = <0>;
13 cpu@0 {
16 reg = <0>;
31 #address-cells = <0>;
41 #clock-cells = <0>;
47 #clock-cells = <0>;
57 ranges = <0 0x10000000 0x01000000>;
61 reg = <0x411400 0x30>, <0x411600 0x30>;
72 reg = <0x403000 0x30>;
81 reg = <0x400000 0xdc>;
[all …]
/freebsd/sys/arm64/broadcom/genet/
H A Dif_genetreg.h38 #define GENET_SYS_REV_CTRL 0x000
41 #define REV_MAJOR 0xf000000
44 #define REV_MINOR 0xf0000
46 #define REV_PHY 0xffff
47 #define GENET_SYS_PORT_CTRL 0x004
49 #define GENET_SYS_RBUF_FLUSH_CTRL 0x008
51 #define GENET_SYS_TBUF_FLUSH_CTRL 0x00c
52 #define GENET_EXT_RGMII_OOB_CTRL 0x08c
57 #define GENET_INTRL2_CPU_STAT 0x200
58 #define GENET_INTRL2_CPU_CLEAR 0x208
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/freebsd/sys/dev/bhnd/siba/
H A Dsibareg.h47 #define SIBA_ENUM_SIZE 0x00100000 /**< size of the enumeration space */
64 * [0x0000-0x0dff] core registers
65 * [0x0e00-0x0eff] SIBA_R1 registers (sonics >= 2.3)
66 * [0x0f00-0x0fff] SIBA_R0 registers
69 #define SIBA_CFG0_OFFSET 0xf00 /**< first configuration block */
70 #define SIBA_CFG1_OFFSET 0xe00 /**< second configuration block (sonics >= 2.3) */
71 #define SIBA_CFG_SIZE 0x100 /**< cfg register block size */
83 #define SIBA_CFG0_IPSFLAG 0x08 /**< initiator port ocp slave flag */
84 #define SIBA_CFG0_TPSFLAG 0x18 /**< target port ocp slave flag */
85 #define SIBA_CFG0_TMERRLOGA 0x48 /**< sonics >= 2.3 */
[all …]
/freebsd/sys/contrib/dev/iwlwifi/
H A Diwl-prph.h15 #define PRPH_BASE (0x00000)
16 #define PRPH_END (0xFFFFF)
19 #define APMG_BASE (PRPH_BASE + 0x3000)
20 #define APMG_CLK_CTRL_REG (APMG_BASE + 0x0000)
21 #define APMG_CLK_EN_REG (APMG_BASE + 0x0004)
22 #define APMG_CLK_DIS_REG (APMG_BASE + 0x0008)
23 #define APMG_PS_CTRL_REG (APMG_BASE + 0x000c)
24 #define APMG_PCIDEV_STT_REG (APMG_BASE + 0x0010)
25 #define APMG_RFKILL_REG (APMG_BASE + 0x0014)
26 #define APMG_RTC_INT_STT_REG (APMG_BASE + 0x001c)
[all …]
/freebsd/sys/sys/
H A Dkernel.h96 SI_SUB_DUMMY = 0x0000000, /* not executed; for linker */
97 SI_SUB_TUNABLES = 0x0700000, /* establish tunable values */
98 SI_SUB_COPYRIGHT = 0x0800001, /* first use of console */
99 SI_SUB_VM = 0x1000000, /* virtual memory system init */
100 SI_SUB_COUNTER = 0x1100000, /* counter(9) is initialized */
101 SI_SUB_KMEM = 0x1800000, /* kernel memory */
102 SI_SUB_HYPERVISOR = 0x1A40000, /*
107 SI_SUB_WITNESS = 0x1A80000, /* witness initialization */
108 SI_SUB_MTX_POOL_DYNAMIC = 0x1AC0000, /* dynamic mutex pool */
109 SI_SUB_LOCK = 0x1B00000, /* various locks */
[all …]
/freebsd/sys/riscv/starfive/
H A Djh7110_pcie.c45 #define IRQ_LOCAL_MASK 0x180
46 #define IRQ_LOCAL_STATUS 0x184
47 #define IRQ_MSI_BASE 0x190
48 #define IRQ_MSI_STATUS 0x194
50 #define MSI_MASK 0x10000000
51 #define INTX_MASK 0xf000000
52 #define ERROR_MASK 0x80770000
55 #define MSI_USED 0x1
56 #define MSI_PCIE0_MASK_OFFSET 0xa0;
57 #define MSI_PCIE1_MASK_OFFSET 0xf0;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dqdu1000.dtsi26 #size-cells = <0>;
28 CPU0: cpu@0 {
31 reg = <0x0 0x0>;
32 clocks = <&cpufreq_hw 0>;
36 qcom,freq-domains = <&cpufreq_hw 0>;
54 reg = <0x0 0x100>;
55 clocks = <&cpufreq_hw 0>;
59 qcom,freq-domains = <&cpufreq_hw 0>;
72 reg = <0x0 0x200>;
73 clocks = <&cpufreq_hw 0>;
[all …]
/freebsd/sys/dev/hptmv/
H A Dentry.c63 int hpt_dbg_level = 0;
99 __DRIVER_MODULE(PROC_DIR_NAME, pci, hpt_pci_driver, 0, 0);
150 UCHAR DPC_Request_Nums = 0;
152 static int DpcQueue_First=0;
153 static int DpcQueue_Last = 0;
181 pVDev->u.disk.df_on_line = 0; in failDevice()
182 pVDev->vf_online = 0; in failDevice()
240 * Return: 0 on success, otherwise on failure
267 KdPrint(("requestQueue addr is 0x%llX", (HPT_U64)(ULONG_PTR)req_dma_addr)); in hptmv_init_channel()
270 if (req_dma_addr & 0x3ff) in hptmv_init_channel()
[all …]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300reg.h34 #define AR_CR_LP_RXE 0x00000004 // Receive LPQ enable
35 #define AR_CR_HP_RXE 0x00000008 // Receive HPQ enable
36 #define AR_CR_RXD 0x00000020 // Receive disable
37 #define AR_CR_SWI 0x00000040 // One-shot software interrupt
42 #define AR_CFG_SWTD 0x00000001 // byteswap tx descriptor words
43 #define AR_CFG_SWTB 0x00000002 // byteswap tx data buffer words
44 #define AR_CFG_SWRD 0x00000004 // byteswap rx descriptor words
45 #define AR_CFG_SWRB 0x00000008 // byteswap rx data buffer words
46 #define AR_CFG_SWRG 0x00000010 // byteswap register access data words
47 #define AR_CFG_AP_ADHOC_INDICATION 0x00000020 // AP/adhoc indication (0-AP 1-Adhoc)
[all …]
/freebsd/sys/dev/bnxt/bnxt_en/
H A Dhsi_struct_def.h71 * * 0x0-0xFFF8 - The function ID
72 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
73 * * 0xFFFD - Reserved for user-space HWRM interface
74 * * 0xFFFF - HWRM
104 #define CMD_DISCR_TLV_ENCAP UINT32_C(0x8000)
109 #define TLV_TYPE_HWRM_REQUEST UINT32_C(0x1)
111 #define TLV_TYPE_HWRM_RESPONSE UINT32_C(0x2)
113 #define TLV_TYPE_ROCE_SP_COMMAND UINT32_C(0x3)
115 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0x4)
117 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0x5)
[all …]