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/linux/Documentation/devicetree/bindings/mtd/partitions/
H A Dlinksys,ns-partitions.yaml34 "^partition@[0-9a-f]+$":
56 partition@0 {
58 reg = <0x0 0x100000>;
64 reg = <0x100000 0x100000>;
69 reg = <0x200000 0xf00000>;
74 reg = <0x1100000 0xf00000>;
H A Dbrcm,bcm4908-partitions.yaml33 "^partition@[0-9a-f]+$":
53 partition@0 {
55 reg = <0x0 0x100000>;
60 reg = <0x100000 0xf00000>;
65 reg = <0x1000000 0xf00000>;
70 reg = <0x1f00000 0x100000>;
H A Dfixed-partitions.yaml51 "@[0-9a-f]+$":
77 partition@0 {
79 reg = <0x0000000 0x100000>;
84 reg = <0x0100000 0x200000>;
96 partition@0 {
98 reg = <0x00000000 0x1 0x00000000>;
110 partition@0 {
112 reg = <0x0 0x00000000 0x2 0x00000000>;
118 reg = <0x2 0x00000000 0x1 0x00000000>;
128 partition@0 {
[all …]
H A Dbinman.yaml43 reg = <0x100000 0xf00000>;
44 align-size = <0x1000>;
45 align-end = <0x10000>;
50 reg = <0x200000 0x100000>;
51 align = <0x4000>;
H A Dnvmem-cells.yaml45 reg = <0x1200000 0x0140000>;
51 macaddr_gmac1: macaddr_gmac1@0 {
52 reg = <0x0 0x6>;
56 reg = <0x6 0x6>;
60 reg = <0x1000 0x2f20>;
64 reg = <0x5000 0x2f20>;
73 partition@0 {
75 reg = <0x000000 0x100000>;
82 reg = <0x100000 0xe00000>;
88 reg = <0xf00000 0x100000>;
[all …]
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-80x0.dtsi24 #define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))
25 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
45 #define CP11X_PCIEx_MEM_BASE(iface) (0xfa000000 + (iface * 0x1000000))
46 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
H A Dcn9130.dtsi29 #define CP11X_PCIEx_MEM_BASE(iface) ((iface == 0) ? 0xc0000000 : \
30 0xe0000000 + ((iface - 1) * 0x1000000))
31 #define CP11X_PCIEx_MEM_SIZE(iface) ((iface == 0) ? 0x1ff00000 : 0xf00000)
H A Darmada-70x0.dtsi22 #define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))
23 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
H A Dac5-98dx35xx-rd.dts30 memory@0 {
32 reg = <0x2 0x00000000 0x0 0x40000000>;
37 #phy-cells = <0>;
42 phy0: ethernet-phy@0 {
43 reg = <0>;
76 spiflash0: flash@0 {
81 reg = <0>;
86 partition@0 {
88 reg = <0x0 0x800000>;
93 reg = <0x800000 0x700000>;
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
H A Dgfx_8_0_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
H A Dgfx_8_1_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_7_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
H A Dgmc_8_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
H A Dgmc_7_0_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MC_RD_ENABLE_MASK 0x30
36 #define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x4
[all …]
H A Dgmc_8_2_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
/linux/drivers/comedi/drivers/
H A Dcomedi_8255.c24 * digital I/O subdevice with 24 channels. The channel 0 corresponds to
25 * the 8255's port A, bit 0; channel 23 corresponds to port C, bit 7.
26 * Direction configuration is done in blocks, with channels 0-7, 8-15,
28 * supported is mode 0.
48 return 0; in subdev_8255_io()
60 return 0; in subdev_8255_mmio()
77 if (mask & 0xff) in subdev_8255_insn()
79 s->state & 0xff, context); in subdev_8255_insn()
80 if (mask & 0xff00) in subdev_8255_insn()
82 (s->state >> 8) & 0xff, context); in subdev_8255_insn()
[all …]
/linux/tools/perf/tests/
H A Dhists_common.h12 #define FAKE_MAP_PERF 0x400000
13 #define FAKE_MAP_BASH 0x400000
14 #define FAKE_MAP_LIBC 0x500000
15 #define FAKE_MAP_KERNEL 0xf00000
16 #define FAKE_MAP_LENGTH 0x100000
/linux/Documentation/devicetree/bindings/pci/
H A Dmarvell,armada8k-pcie.yaml83 reg = <0xf2600000 0x10000>, <0xf6f00000 0x80000>;
92 ranges = <0x81000000 0 0xf9000000 0xf9000000 0 0x10000>, /* downstream I/O */
93 <0x82000000 0 0xf6000000 0xf6000000 0 0xf00000>; /* non-prefetchable memory */
94 interrupt-map-mask = <0 0 0 0>;
95 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_5_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
H A Duvd_6_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
/linux/arch/m68k/include/asm/
H A Ddvma.h23 #define dvma_malloc(x) dvma_malloc_align(x, 0)
24 #define dvma_map(x, y) dvma_map_align(x, y, 0)
25 #define dvma_map_vme(x, y) (dvma_map(x, y) & 0xfffff)
26 #define dvma_map_align_vme(x, y, z) (dvma_map_align (x, y, z) & 0xfffff)
41 #define DVMA_START 0xf00000
42 #define DVMA_END 0xfe0000
47 /* empirical kludge -- dvma regions only seem to work right on 0x10000
49 #define DVMA_REGION_SIZE 0x10000
54 #define dvma_vtop(x) ((unsigned long)(x) & 0xffffff)
55 #define dvma_ptov(x) ((unsigned long)(x) | 0xf000000)
[all …]
/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-cc108.dts29 memory@0 {
31 reg = <0x0 0x20000000>;
36 #phy-cells = <0>;
41 #phy-cells = <0>;
58 flash@0 { /* 16 MB */
60 reg = <0x0>;
66 partition@0 {
68 reg = <0x0 0x400000>; /* 4MB */
72 reg = <0x400000 0x400000>; /* 4MB */
76 reg = <0x800000 0x400000>; /* 4MB */
[all …]
/linux/include/rdma/
H A Dopa_addr.h11 #define OPA_SPECIAL_OUI (0x00066AULL)
14 ? 0 : x)
15 #define OPA_GID_INDEX 0x1
17 * 0xF8 - 4 bits of multicast range and 1 bit for collective range
19 * Multicast range: 0xF00000 to 0xF7FFFF
20 * Collective range: 0xF80000 to 0xFFFFFE
22 #define OPA_MCAST_NR 0x4 /* Number of top bits set */
23 #define OPA_COLLECTIVE_NR 0x1 /* Number of bits after MCAST_NR */
48 return be64_to_cpu(gid->global.interface_id) & 0xFFFFFFFF; in opa_get_lid_from_gid()
/linux/drivers/platform/chrome/
H A Dchromeos_pstore.c59 .mem_size = 0x100000,
60 .mem_address = 0xf00000,
61 .record_size = 0x40000,
62 .console_size = 0x20000,
63 .ftrace_size = 0x20000,
64 .pmsg_size = 0x20000,
77 { "GOOG9999", 0 },
94 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); in chromeos_probe_acpi()
107 return 0; in chromeos_probe_acpi()
124 if (ecc_size > 0) in chromeos_pstore_init()

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