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/linux/arch/arm64/boot/dts/ti/
H A Dk3-am68-sk-som.dtsi16 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
17 <0x00000008 0x80000000 0x00000003 0x80000000>;
26 reg = <0x00 0x9e800000 0x00 0x01800000>;
32 reg = <0x00 0xa0000000 0x00 0x100000>;
38 reg = <0x00 0xa0100000 0x00 0xf00000>;
44 reg = <0x00 0xa1000000 0x00 0x100000>;
50 reg = <0x00 0xa1100000 0x00 0xf00000>;
56 reg = <0x00 0xa2000000 0x00 0x100000>;
62 reg = <0x00 0xa2100000 0x00 0xf00000>;
68 reg = <0x00 0xa3000000 0x00 0x100000>;
[all …]
H A Dk3-j721e-som-p0.dtsi17 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
18 <0x00000008 0x80000000 0x00000000 0x80000000>;
27 reg = <0x00 0x9e800000 0x00 0x01800000>;
28 alignment = <0x1000>;
34 reg = <0x00 0xa0000000 0x00 0x100000>;
40 reg = <0x00 0xa0100000 0x00 0xf00000>;
46 reg = <0x00 0xa1000000 0x00 0x100000>;
52 reg = <0x00 0xa1100000 0x00 0xf00000>;
58 reg = <0x00 0xa2000000 0x00 0x100000>;
64 reg = <0x00 0xa2100000 0x00 0xf00000>;
[all …]
H A Dk3-am68-phycore-som.dtsi28 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
29 <0x00000008 0x80000000 0x00000000 0x80000000>;
42 size = <0x00 0x20000000>;
47 reg = <0x00 0x9e800000 0x00 0x01800000>;
48 alignment = <0x1000>;
54 reg = <0x00 0xa0000000 0x00 0x100000>;
60 reg = <0x00 0xa0100000 0x00 0xf00000>;
66 reg = <0x00 0xa1000000 0x00 0x100000>;
72 reg = <0x00 0xa1100000 0x00 0xf00000>;
78 reg = <0x00 0xa2000000 0x00 0x100000>;
[all …]
H A Dk3-j721s2-som-p0.dtsi18 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
19 <0x00000008 0x80000000 0x00000003 0x80000000>;
29 reg = <0x00 0x9e800000 0x00 0x01800000>;
30 alignment = <0x1000>;
36 reg = <0x00 0xa0000000 0x00 0x100000>;
42 reg = <0x00 0xa0100000 0x00 0xf00000>;
48 reg = <0x00 0xa1000000 0x00 0x100000>;
54 reg = <0x00 0xa1100000 0x00 0xf00000>;
60 reg = <0x00 0xa2000000 0x00 0x100000>;
66 reg = <0x00 0xa2100000 0x00 0xf00000>;
[all …]
H A Dk3-am642-tqma64xxl.dtsi19 reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
29 reg = <0x00 0x9e800000 0x00 0x01800000>;
30 alignment = <0x1000>;
36 reg = <0x00 0xa0000000 0x00 0x100000>;
42 reg = <0x00 0xa0100000 0x00 0xf00000>;
48 reg = <0x00 0xa1000000 0x00 0x100000>;
54 reg = <0x00 0xa1100000 0x00 0xf00000>;
60 reg = <0x00 0xa2000000 0x00 0x100000>;
66 reg = <0x00 0xa2100000 0x00 0xf00000>;
72 reg = <0x00 0xa3000000 0x00 0x100000>;
[all …]
H A Dk3-am64-phycore-som.dtsi29 reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
39 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
40 alignment = <0x1000>;
46 reg = <0x00 0xa0000000 0x00 0x100000>;
52 reg = <0x00 0xa0100000 0x00 0xf00000>;
58 reg = <0x00 0xa1000000 0x00 0x100000>;
64 reg = <0x00 0xa1100000 0x00 0xf00000>;
70 reg = <0x00 0xa2000000 0x00 0x100000>;
76 reg = <0x00 0xa2100000 0x00 0xf00000>;
82 reg = <0x00 0xa3000000 0x00 0x100000>;
[all …]
H A Dk3-am69-sk.dts38 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
39 <0x00000008 0x80000000 0x00000007 0x80000000>;
48 reg = <0x00 0x9e800000 0x00 0x01800000>;
54 reg = <0x00 0xa0000000 0x00 0x100000>;
60 reg = <0x00 0xa0100000 0x00 0xf00000>;
66 reg = <0x00 0xa1000000 0x00 0x100000>;
72 reg = <0x00 0xa1100000 0x00 0xf00000>;
78 reg = <0x00 0xa2000000 0x00 0x100000>;
84 reg = <0x00 0xa2100000 0x00 0xf00000>;
90 reg = <0x00 0xa3000000 0x00 0x100000>;
[all …]
H A Dk3-j721e-beagleboneai64.dts40 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
41 <0x00000008 0x80000000 0x00000000 0x80000000>;
50 reg = <0x00 0x9e800000 0x00 0x01800000>;
56 reg = <0x00 0xa0000000 0x00 0x100000>;
62 reg = <0x00 0xa0100000 0x00 0xf00000>;
68 reg = <0x00 0xa1000000 0x00 0x100000>;
74 reg = <0x00 0xa1100000 0x00 0xf00000>;
80 reg = <0x00 0xa2000000 0x00 0x100000>;
86 reg = <0x00 0xa2100000 0x00 0xf00000>;
92 reg = <0x00 0xa3000000 0x00 0x100000>;
[all …]
H A Dk3-am67a-beagley-ai.dts32 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
33 <0x00000008 0x80000000 0x00000000 0x80000000>;
44 reg = <0x00 0x9e780000 0x00 0x80000>;
49 reg = <0x00 0x9e800000 0x00 0x01800000>;
55 reg = <0x00 0xa0000000 0x00 0x100000>;
61 reg = <0x00 0xa0100000 0x00 0xf00000>;
67 reg = <0x00 0xa1000000 0x00 0x100000>;
73 reg = <0x00 0xa1100000 0x00 0xf00000>;
79 reg = <0x00 0xa2000000 0x00 0x100000>;
85 reg = <0x00 0xa2100000 0x00 0xf00000>;
[all …]
H A Dk3-j784s4-j742s2-evm-common.dtsi34 reg = <0x00 0x9e800000 0x00 0x01800000>;
40 reg = <0x00 0xa0000000 0x00 0x100000>;
46 reg = <0x00 0xa0100000 0x00 0xf00000>;
52 reg = <0x00 0xa1000000 0x00 0x100000>;
58 reg = <0x00 0xa1100000 0x00 0xf00000>;
64 reg = <0x00 0xa2000000 0x00 0x100000>;
70 reg = <0x00 0xa2100000 0x00 0xf00000>;
76 reg = <0x00 0xa3000000 0x00 0x100000>;
82 reg = <0x00 0xa3100000 0x00 0xf00000>;
88 reg = <0x00 0xa4000000 0x00 0x100000>;
[all …]
H A Dk3-j7200-som-p0.dtsi17 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
18 <0x00000008 0x80000000 0x00000000 0x80000000>;
27 reg = <0x00 0x9e800000 0x00 0x01800000>;
28 alignment = <0x1000>;
34 reg = <0x00 0xa0000000 0x00 0x100000>;
40 reg = <0x00 0xa0100000 0x00 0xf00000>;
46 reg = <0x00 0xa1000000 0x00 0x100000>;
52 reg = <0x00 0xa1100000 0x00 0xf00000>;
58 reg = <0x00 0xa2000000 0x00 0x100000>;
64 reg = <0x00 0xa2100000 0x00 0xf00000>;
[all …]
H A Dk3-am642-sk.dts40 reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
49 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
50 alignment = <0x1000>;
56 reg = <0x00 0xa0000000 0x00 0x100000>;
62 reg = <0x00 0xa0100000 0x00 0xf00000>;
68 reg = <0x00 0xa1000000 0x00 0x100000>;
74 reg = <0x00 0xa1100000 0x00 0xf00000>;
80 reg = <0x00 0xa2000000 0x00 0x100000>;
86 reg = <0x00 0xa2100000 0x00 0xf00000>;
92 reg = <0x00 0xa3000000 0x00 0x100000>;
[all …]
H A Dk3-j721e-sk.dts36 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
37 <0x00000008 0x80000000 0x00000000 0x80000000>;
46 reg = <0x00 0x9e800000 0x00 0x01800000>;
47 alignment = <0x1000>;
53 reg = <0x00 0xa0000000 0x00 0x100000>;
59 reg = <0x00 0xa0100000 0x00 0xf00000>;
65 reg = <0x00 0xa1000000 0x00 0x100000>;
71 reg = <0x00 0xa1100000 0x00 0xf00000>;
77 reg = <0x00 0xa2000000 0x00 0x100000>;
83 reg = <0x00 0xa2100000 0x00 0xf00000>;
[all …]
H A Dk3-am62a-phycore-som.dtsi31 pinctrl-0 = <&leds_pins_default>;
33 led-0 {
44 reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
57 size = <0x00 0x24000000>;
58 alloc-ranges = <0x00 0xc0000000 0x00 0x24000000>;
64 reg = <0x00 0x99800000 0x00 0x100000>;
70 reg = <0x00 0x99900000 0x00 0xf00000>;
76 reg = <0x00 0x9b800000 0x00 0x100000>;
82 reg = <0x00 0x9b900000 0x00 0xf00000>;
88 reg = <0x00 0x9c800000 0x00 0x100000>;
[all …]
/linux/Documentation/devicetree/bindings/mtd/partitions/
H A Dlinksys,ns-partitions.yaml34 "^partition@[0-9a-f]+$":
56 partition@0 {
58 reg = <0x0 0x100000>;
64 reg = <0x100000 0x100000>;
69 reg = <0x200000 0xf00000>;
74 reg = <0x1100000 0xf00000>;
H A Dbrcm,bcm4908-partitions.yaml33 "^partition@[0-9a-f]+$":
53 partition@0 {
55 reg = <0x0 0x100000>;
60 reg = <0x100000 0xf00000>;
65 reg = <0x1000000 0xf00000>;
70 reg = <0x1f00000 0x100000>;
H A Dfixed-partitions.yaml51 "@[0-9a-f]+$":
77 partition@0 {
79 reg = <0x0000000 0x100000>;
84 reg = <0x0100000 0x200000>;
96 partition@0 {
98 reg = <0x00000000 0x1 0x00000000>;
110 partition@0 {
112 reg = <0x0 0x00000000 0x2 0x00000000>;
118 reg = <0x2 0x00000000 0x1 0x00000000>;
128 partition@0 {
[all …]
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-80x0.dtsi24 #define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))
25 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
45 #define CP11X_PCIEx_MEM_BASE(iface) (0xfa000000 + (iface * 0x1000000))
46 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
H A Dcn9130.dtsi29 #define CP11X_PCIEx_MEM_BASE(iface) ((iface == 0) ? 0xc0000000 : \
30 0xe0000000 + ((iface - 1) * 0x1000000))
31 #define CP11X_PCIEx_MEM_SIZE(iface) ((iface == 0) ? 0x1ff00000 : 0xf00000)
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
H A Dgfx_8_0_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
H A Dgfx_8_1_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_7_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
H A Dgmc_8_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
H A Dgmc_7_0_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MC_RD_ENABLE_MASK 0x30
36 #define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x4
[all …]

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