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/freebsd/sys/dev/e1000/
H A De1000_82541.h42 #define IGP01E1000_PHY_AGC_A 0x1172
43 #define IGP01E1000_PHY_AGC_B 0x1272
44 #define IGP01E1000_PHY_AGC_C 0x1472
45 #define IGP01E1000_PHY_AGC_D 0x1872
47 #define IGP01E1000_PHY_AGC_PARAM_A 0x1171
48 #define IGP01E1000_PHY_AGC_PARAM_B 0x1271
49 #define IGP01E1000_PHY_AGC_PARAM_C 0x1471
50 #define IGP01E1000_PHY_AGC_PARAM_D 0x1871
52 #define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000
53 #define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000
[all …]
/freebsd/contrib/llvm-project/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/
H A DRuntimeDyldMachOARM.h3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
46 Addr |= 0x1; in modifyAddressBasedOnFlags()
71 Temp &= 0x00ffffff; // Mask out the opcode. in decodeAddend()
79 // Encoding for high bits 1111 0XXX XXXX XXXX in decodeAddend()
82 if ((HighInsn & 0xf800) != 0xf000) in decodeAddend()
88 if ((LowInsn & 0xf800) != 0xf800) in decodeAddend()
93 return SignExtend64<23>(((HighInsn & 0x7ff) << 12) | in decodeAddend()
94 ((LowInsn & 0x7ff) << 1)); in decodeAddend()
221 assert((HighInsn & 0xf800) == 0xf000 && in resolveRelocation()
223 HighInsn = (HighInsn & 0xf800) | ((Value >> 12) & 0x7ff); in resolveRelocation()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreMachineFunctionInfo.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
34 // The arbitrary value of 0xf000 allows frames of up to ~240KB before spill in isLargeFrame()
38 return CachedEStackSize > 0xf000; in isLargeFrame()
49 // A fixed offset of 0 allows us to save / restore LR using entsp / retsp. in createLRSpillSlot()
50 LRSpillSlot = MFI.CreateFixedObject(TRI.getSpillSize(RC), 0, true); in createLRSpillSlot()
81 EHSpillSlot[0] = MFI.CreateStackObject(Size, Alignment, true); in createEHSpillSlot()
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dmpc8544ds.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x800000>;
44 partition@0 {
45 reg = <0x0 0x10000>;
50 reg = <0x20000 0x30000>;
56 reg = <0x200000 0x200000>;
62 reg = <0x400000 0x380000>;
67 reg = <0x780000 0x80000>;
82 phy0: ethernet-phy@0 {
83 interrupts = <10 1 0 0>;
[all …]
H A Dp2020ds.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x8000000>;
44 ramdisk@0 {
45 reg = <0x0 0x03000000>;
50 reg = <0x03000000 0x00e00000>;
55 reg = <0x03e00000 0x00200000>;
60 reg = <0x04000000 0x00400000>;
65 reg = <0x04400000 0x03b00000>;
69 reg = <0x07f00000 0x00080000>;
74 reg = <0x07f80000 0x00080000>;
[all …]
H A Dmpc8641_hpcn_36b.dts18 reg = <0x0 0x00000000 0x0 0x40000000>; // 1G at 0x0
22 reg = <0x0f 0xffe05000 0x0 0x1000>;
24 ranges = <0 0 0xf 0xef800000 0x00800000
25 2 0 0xf 0xffdf8000 0x00008000
26 3 0 0xf 0xffdf0000 0x00008000>;
28 flash@0,0 {
30 reg = <0 0 0x00800000>;
35 partition@0 {
37 reg = <0x00000000 0x00300000>;
41 reg = <0x00300000 0x00100000>;
[all …]
H A Dmpc8641_hpcn.dts16 reg = <0x00000000 0x40000000>; // 1G at 0x0
20 reg = <0xffe05000 0x1000>;
22 ranges = <0 0 0xef800000 0x00800000
23 2 0 0xffdf8000 0x00008000
24 3 0 0xffdf0000 0x00008000>;
26 flash@0,0 {
28 reg = <0 0 0x00800000>;
33 partition@0 {
35 reg = <0x00000000 0x00300000>;
39 reg = <0x00300000 0x00100000>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/misc/
H A Dnvidia,tegra186-misc.yaml41 reg = <0x00100000 0xf000>,
42 <0x0010f000 0x1000>;
/freebsd/sys/dev/syscons/
H A Dscvgarndr.c54 #define SC_RENDER_DEBUG 0
108 RENDERER(mda, 0, txtrndrsw, vga_set);
109 RENDERER(cga, 0, txtrndrsw, vga_set);
110 RENDERER(ega, 0, txtrndrsw, vga_set);
111 RENDERER(vga, 0, txtrndrsw, vga_set);
161 0xC000, 0xA000, 0x9000, 0x8800, 0x8400, 0x8200, 0x8100, 0x8200,
162 0x8400, 0x8400, 0x8400, 0x9200, 0xB200, 0xA900, 0xC900, 0x8600, }, {
163 0x0000, 0x4000, 0x6000, 0x7000, 0x7800, 0x7C00, 0x7E00, 0x7C00,
164 0x7800, 0x7800, 0x7800, 0x6C00, 0x4C00, 0x4600, 0x0600, 0x0000, },
169 0xC000, 0xA000, 0x9000, 0x8800, 0x8400, 0x8200, 0x8100, 0x8700,
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/mediatek/
H A Dmediatek,ccorr.yaml79 reg = <0 0x1400f000 0 0x1000>;
83 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
/freebsd/sys/dev/safexcel/
H A Dsafexcel_reg.h30 #define SAFEXCEL_HIA_VERSION_LE 0x35ca
31 #define SAFEXCEL_HIA_VERSION_BE 0xca35
32 #define EIP201_VERSION_LE 0x36c9
33 #define SAFEXCEL_REG_LO16(_reg) ((_reg) & 0xffff)
34 #define SAFEXCEL_REG_HI16(_reg) (((_reg) >> 16) & 0xffff)
37 #define CDR_BASE_ADDR_LO(x) (0x0 + ((x) << 12))
38 #define CDR_BASE_ADDR_HI(x) (0x4 + ((x) << 12))
39 #define CDR_DATA_BASE_ADDR_LO(x) (0x8 + ((x) << 12))
40 #define CDR_DATA_BASE_ADDR_HI(x) (0xC + ((x) << 12))
41 #define CDR_ACD_BASE_ADDR_LO(x) (0x10 + ((x) << 12))
[all …]
/freebsd/sys/dev/mii/
H A Djmphyreg.h38 #define JMPHY_SSR 0x11
39 #define JMPHY_SSR_SPEED_1000 0x8000
40 #define JMPHY_SSR_SPEED_100 0x4000
41 #define JMPHY_SSR_SPEED_10 0x0000
42 #define JMPHY_SSR_SPEED_MASK 0xC000
43 #define JMPHY_SSR_DUPLEX 0x2000
44 #define JMPHY_SSR_SPD_DPLX_RESOLVED 0x0800
45 #define JMPHY_SSR_LINK_UP 0x0400
46 #define JMPHY_SSR_MDI_XOVER 0x0040
47 #define JMPHY_SSR_INV_POLARITY 0x0002
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/freebsd/sys/dev/adb/
H A Dadb_bus.c68 { 0, 0 },
81 return (0); in adb_bus_probe()
97 if (config_intrhook_establish(&sc->enum_hook) != 0) in adb_bus_attach()
100 return (0); in adb_bus_attach()
115 sc->packet_reply = 0; in adb_bus_enumerate()
116 sc->autopoll_mask = 0; in adb_bus_enumerate()
117 sc->sync_packet = 0xffff; in adb_bus_enumerate()
120 for (i = 0; i < 16; i++) { in adb_bus_enumerate()
122 sc->devinfo[i].default_address = 0; in adb_bus_enumerate()
126 adb_send_raw_packet_sync(dev,0,ADB_COMMAND_BUS_RESET,0,0,NULL,NULL); in adb_bus_enumerate()
[all …]
/freebsd/sys/dev/qlxge/
H A Dqls_isr.c69 ha->tx_ring[txr_idx].txr_done = 0; in qls_tx_comp()
89 if (qls_get_mbuf(ha, rxb, NULL) != 0) { in qls_replenish_rx()
91 "%s: qls_get_mbuf [0,%d,%d] failed\n", in qls_replenish_rx()
105 rxr->sbq_next = 0; in qls_replenish_rx()
114 rxr->sbq_free = 0; in qls_replenish_rx()
160 if ((cq_e->flags1 & Q81_RX_FLAGS1_ERR_MASK) == 0) { in qls_rx_comp()
194 mp->m_pkthdr.csum_flags = 0; in qls_rx_comp()
199 mp->m_pkthdr.csum_data = 0xFFFF; in qls_rx_comp()
204 if (lro->lro_cnt && (tcp_lro_rx(lro, mp, 0) == 0)) { in qls_rx_comp()
213 device_printf(dev, "%s: err [0%08x]\n", __func__, cq_e->flags1); in qls_rx_comp()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/ExecutionEngine/JITLink/
H A Daarch32.h3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
116 ThumbSymbol = 1 << 0, in getArmConfigForCPUArch()
137 Undefined = 0,
165 constexpr HalfWords() : Hi(0), Lo(0) {}
206 static constexpr uint32_t Opcode = 0x0a000000;
207 static constexpr uint32_t ImmMask = 0x00ffffff;
211 static constexpr uint32_t OpcodeMask = 0x0f000000;
215 static constexpr uint32_t OpcodeMask = 0x0e000000;
216 static constexpr uint32_t CondMask = 0xe000000
[all...]
/freebsd/contrib/opencsd/decoder/source/ete/
H A Dtrc_cmp_cfg_ete.cpp39 m_ete_cfg.reg_idr0 = 0x28000EA1; in ETEConfig()
40 m_ete_cfg.reg_idr1 = 0x4100FFF3; in ETEConfig()
41 m_ete_cfg.reg_idr2 = 0x00000488; in ETEConfig()
42 m_ete_cfg.reg_idr8 = 0; in ETEConfig()
43 m_ete_cfg.reg_configr = 0xC1; in ETEConfig()
44 m_ete_cfg.reg_traceidr = 0; in ETEConfig()
47 m_ete_cfg.reg_devarch = 0x47705A13; in ETEConfig()
83 m_cfg.reg_idr9 = 0; in copyV4()
84 m_cfg.reg_idr10 = 0; in copyV4()
85 m_cfg.reg_idr11 = 0; in copyV4()
[all …]
/freebsd/contrib/pf/libevent/
H A Devent.h44 #define EVLIST_TIMEOUT 0x01
45 #define EVLIST_INSERTED 0x02
46 #define EVLIST_SIGNAL 0x04
47 #define EVLIST_ACTIVE 0x08
48 #define EVLIST_INTERNAL 0x10
49 #define EVLIST_INIT 0x80
51 /* EVLIST_X_ Private space: 0x1000-0xf000 */
52 #define EVLIST_ALL (0xf000 | 0x9f)
54 #define EV_TIMEOUT 0x01
55 #define EV_READ 0x02
[all …]
/freebsd/sys/dev/qat/include/
H A Dicp_qat_fw_init_admin.h9 ICP_QAT_FW_INIT_ME = 0,
31 ICP_QAT_FW_INIT_RESP_STATUS_SUCCESS = 0,
37 CNV_ERR_TYPE_NO_ERROR = 0,
56 ((s16)((_lerror & 0x0FFF) | (_lerror & 0x0800 ? 0xF000 : 0))); \
58 #define CNV_ERROR_DECOMP_STATUS_GET(latest_error) ((s8)(latest_error & 0xFF))
195 enum icp_qat_fw_init_admin_init_flag { ICP_QAT_FW_INIT_FLAG_PKE_DISABLED = 0 };
202 #define ICP_QAT_FW_COMN_HEARTBEAT_OK 0
204 #define ICP_QAT_FW_COMN_HEARTBEAT_FLAG_BITPOS 0
205 #define ICP_QAT_FW_COMN_HEARTBEAT_FLAG_MASK 0x1
206 #define ICP_QAT_FW_COMN_STATUS_RESRVD_FLD_MASK 0xFE
/freebsd/sys/dev/virtio/pci/
H A Dvirtio_pci.h52 #define VTPCI_FLAG_NO_MSI 0x0001
53 #define VTPCI_FLAG_NO_MSIX 0x0002
54 #define VTPCI_FLAG_MODERN 0x0004
55 #define VTPCI_FLAG_INTX 0x1000
56 #define VTPCI_FLAG_MSI 0x2000
57 #define VTPCI_FLAG_MSIX 0x4000
58 #define VTPCI_FLAG_SHARED_MSIX 0x8000
59 #define VTPCI_FLAG_ITYPE_MASK 0xF000
91 return ((cn->vtpci_flags & VTPCI_FLAG_NO_MSIX) == 0); in vtpci_is_msix_available()
97 return ((cn->vtpci_flags & VTPCI_FLAG_MSIX) != 0); in vtpci_is_msix_enabled()
[all …]
/freebsd/sys/dev/ic/
H A Di82586.h64 #define IE_SCP_ADDR 0xfffff4
93 #define IE_RU_COMMAND 0x0070 /* mask for RU command */
94 #define IE_RU_NOP 0 /* for completeness */
95 #define IE_RU_START 0x0010 /* start receive unit command */
96 #define IE_RU_ENABLE 0x0020 /* enable receiver command */
97 #define IE_RU_DISABLE 0x0030 /* disable receiver command */
98 #define IE_RU_ABORT 0x0040 /* abort current receive operation */
100 #define IE_CU_COMMAND 0x0700 /* mask for CU command */
101 #define IE_CU_NOP 0 /* included for completeness */
102 #define IE_CU_START 0x0100 /* do-command command */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dqcom,msm8916-wcd-analog.txt61 reg = <0xf000 0x200>;
68 interrupts = <0x1 0xf0 0x0 IRQ_TYPE_NONE>,
69 <0x1 0xf0 0x1 IRQ_TYPE_NONE>,
70 <0x1 0xf0 0x2 IRQ_TYPE_NONE>,
71 <0x1 0xf0 0x3 IRQ_TYPE_NONE>,
72 <0x1 0xf0 0x4 IRQ_TYPE_NONE>,
73 <0x1 0xf0 0x5 IRQ_TYPE_NONE>,
74 <0x1 0xf0 0x6 IRQ_TYPE_NONE>,
75 <0x1 0xf0 0x7 IRQ_TYPE_NONE>,
76 <0x1 0xf1 0x0 IRQ_TYPE_NONE>,
[all …]
/freebsd/sys/dev/sdhci/
H A Dsdhci_xenon.h36 #define XENON_SYS_OP_CTRL 0x0108
40 #define XENON_SYS_EXT_OP_CTRL 0x010C
43 #define XENON_SLOT_EMMC_CTRL 0x0130
48 #define XENON_CTRL2_MMC_HS200 0x5
49 #define XENON_CTRL2_MMC_HS400 0x6
52 #define XENON_EMMC_PHY_REG_BASE 0x170
59 #define XENON_WAIT_CYCLE_BEFORE_USING_MASK 0xF
61 #define XENON_FC_SYNC_EN_DURATION_MASK 0xF
63 #define XENON_FC_SYNC_RST_EN_DURATION_MASK 0xF
65 #define XENON_FC_SYNC_RST_DURATION_MASK 0xF
[all …]
/freebsd/sys/dev/mwl/
H A Dmwldiag.h46 MWL_DIAG_CMD_REVS = 0, /* MAC/PHY/Radio revs */
74 #define MWL_DIAG_BASE_MAC 0xa000
76 (MWL_DIAG_BASE_MAC <= (r) && (r) < (MWL_DIAG_BASE_MAC+0x1000))
77 #define MWL_DIAG_BASE_BB 0xe000
79 (MWL_DIAG_BASE_BB <= (r) && (r) < (MWL_DIAG_BASE_BB+0x1000))
80 #define MWL_DIAG_BASE_RF 0xf000
82 (MWL_DIAG_BASE_RF <= (r) && (r) < (MWL_DIAG_BASE_RF+0x1000))
96 #define MWL_DIAG_DYN 0x8000 /* allocate buffer in caller */
97 #define MWL_DIAG_IN 0x4000 /* copy in parameters */
98 #define MWL_DIAG_OUT 0x0000 /* copy out results (always) */
[all …]
/freebsd/sys/ofed/include/uapi/rdma/
H A Dib_user_ioctl_cmds.h36 #define UVERBS_ID_NS_MASK 0xF000
/freebsd/sys/dev/ioat/
H A Dioat_hw.h31 #define IOAT_CHANCNT_OFFSET 0x00
33 #define IOAT_XFERCAP_OFFSET 0x01
34 /* Only bits [4:0] are valid. */
35 #define IOAT_XFERCAP_VALID_MASK 0x1f
37 #define IOAT_GENCTRL_OFFSET 0x02
39 #define IOAT_INTRCTRL_OFFSET 0x03
40 #define IOAT_INTRCTRL_MASTER_INT_EN 0x01
42 #define IOAT_ATTNSTATUS_OFFSET 0x04
44 #define IOAT_CBVER_OFFSET 0x08
46 #define IOAT_INTRDELAY_OFFSET 0x0C
[all …]

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