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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dmsi.txt86 reg = <0xa 0xf00>;
93 reg = <0xb 0xf00>;
101 reg = <0xc 0xf00>;
108 dev@0 {
109 reg = <0x0 0xf00>;
117 reg = <0x1 0xf00>;
123 msi-parent = <&msi_a>, <&msi_b 0x17>;
127 reg = <0x2 0xf00>;
133 msi-parent = <&msi_a>, <&msi_b 0x17>, <&msi_c 0x53>;
/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt2701.c38 /* 0E4E8SR 4/8/12/16 */
40 /* 0E2E4SR 2/4/6/8 */
43 MTK_DRV_GRP(2, 16, 0, 2, 2)
47 MTK_PIN_DRV_GRP(0, 0xf50, 0, 1),
48 MTK_PIN_DRV_GRP(1, 0xf50, 0, 1),
49 MTK_PIN_DRV_GRP(2, 0xf50, 0, 1),
50 MTK_PIN_DRV_GRP(3, 0xf50, 0, 1),
51 MTK_PIN_DRV_GRP(4, 0xf50, 0, 1),
52 MTK_PIN_DRV_GRP(5, 0xf50, 0, 1),
53 MTK_PIN_DRV_GRP(6, 0xf50, 0, 1),
[all …]
/linux/drivers/regulator/
H A Dmt6358-regulator.c54 .enable_mask = BIT(0), \
58 .qi = BIT(0), \
82 .vsel_mask = GENMASK(3, 0), \
107 .enable_mask = BIT(0), \
112 .qi = BIT(0), \
127 .vsel_mask = GENMASK(3, 0), \
155 .enable_mask = BIT(0), \
159 .qi = BIT(0), \
183 .vsel_mask = GENMASK(3, 0), \
208 .enable_mask = BIT(0), \
[all …]
H A Dmt6357-regulator.c53 .enable_mask = BIT(0), \
75 .enable_mask = BIT(0), \
96 .enable_mask = BIT(0), \
99 .da_vsel_mask = 0x7f00, \
114 .enable_mask = BIT(0), \
134 if (ret != 0) { in mt6357_get_buck_voltage_sel()
178 0,
186 0,
188 0,
189 0,
[all …]
/linux/drivers/net/ethernet/moxa/
H A Dmoxart_ether.h18 #define TX_REG_OFFSET_DESC0 0
23 #define RX_REG_OFFSET_DESC0 0
28 #define TX_DESC0_PKT_LATE_COL 0x1 /* abort, late collision */
29 #define TX_DESC0_RX_PKT_EXS_COL 0x2 /* abort, >16 collisions */
30 #define TX_DESC0_DMA_OWN 0x80000000 /* owned by controller */
31 #define TX_DESC1_BUF_SIZE_MASK 0x7ff
32 #define TX_DESC1_LTS 0x8000000 /* last TX packet */
33 #define TX_DESC1_FTS 0x10000000 /* first TX packet */
34 #define TX_DESC1_FIFO_COMPLETE 0x20000000
35 #define TX_DESC1_INTR_COMPLETE 0x40000000
[all …]
/linux/drivers/media/pci/ddbridge/
H A Dddbridge-hw.c16 .base = 0x200,
17 .num = 0x08,
18 .size = 0x10,
22 .base = 0x280,
23 .num = 0x08,
24 .size = 0x10,
28 .base = 0x300,
29 .num = 0x08,
30 .size = 0x10,
34 .base = 0x2000,
[all …]
/linux/arch/arm/mm/
H A Dtlb-v4wbi.S35 mov r3, #0
36 mcr p15, 0, r3, c7, c10, 4 @ drain WB
38 bic r0, r0, #0x0ff
39 bic r0, r0, #0xf00
41 mcrne p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
42 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
50 mov r3, #0
51 mcr p15, 0, r3, c7, c10, 4 @ drain WB
52 bic r0, r0, #0x0ff
53 bic r0, r0, #0xf00
[all …]
H A Dtlb-fa.S40 mov r3, #0
41 mcr p15, 0, r3, c7, c10, 4 @ drain WB
42 bic r0, r0, #0x0ff
43 bic r0, r0, #0xf00
44 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
48 mcr p15, 0, r3, c7, c10, 4 @ data write barrier
54 mov r3, #0
55 mcr p15, 0, r3, c7, c10, 4 @ drain WB
56 bic r0, r0, #0x0ff
57 bic r0, r0, #0xf00
[all …]
H A Dtlb-v4wb.S37 mcr p15, 0, r3, c7, c10, 4 @ drain WB
39 mcrne p15, 0, r3, c8, c5, 0 @ invalidate I TLB
40 bic r0, r0, #0x0ff
41 bic r0, r0, #0xf00
42 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
59 mov r3, #0
60 mcr p15, 0, r3, c7, c10, 4 @ drain WB
61 bic r0, r0, #0x0ff
62 bic r0, r0, #0xf00
63 mcr p15, 0, r3, c8, c5, 0 @ invalidate I TLB
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_7_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
H A Dgmc_8_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
H A Dgmc_8_2_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_5_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
H A Duvd_6_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_0_sh_mask.h27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
[all …]
H A Doss_2_4_sh_mask.h27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
[all …]
/linux/arch/powerpc/sysdev/
H A Dindirect_pci.c23 u8 cfg_type = 0; in __indirect_read_config()
29 if (devfn != 0) in __indirect_read_config()
45 reg = ((offset & 0xf00) << 16) | (offset & 0xfc); in __indirect_read_config()
47 reg = offset & 0xfc; in __indirect_read_config()
50 out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) | in __indirect_read_config()
53 out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) | in __indirect_read_config()
89 u8 cfg_type = 0; in indirect_write_config()
95 if (devfn != 0) in indirect_write_config()
111 reg = ((offset & 0xf00) << 16) | (offset & 0xfc); in indirect_write_config()
113 reg = offset & 0xfc; in indirect_write_config()
[all …]
/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Ddcore0_hmmu0_mmu_masks.h24 #define DCORE0_HMMU0_MMU_MMU_ENABLE_R_SHIFT 0
25 #define DCORE0_HMMU0_MMU_MMU_ENABLE_R_MASK 0x1
28 #define DCORE0_HMMU0_MMU_FORCE_ORDERING_WEAK_ORDERING_SHIFT 0
29 #define DCORE0_HMMU0_MMU_FORCE_ORDERING_WEAK_ORDERING_MASK 0x1
31 #define DCORE0_HMMU0_MMU_FORCE_ORDERING_STRONG_ORDERING_MASK 0x2
34 #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_VA_ORDERING_EN_SHIFT 0
35 #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_VA_ORDERING_EN_MASK 0x1
37 #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_CLEAN_LINK_LIST_MASK 0x2
39 #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_HOP_OFFSET_EN_MASK 0x4
41 #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_OBI_ORDERING_EN_MASK 0x8
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_5_1_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x2
36 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dmtk-btcvsd-snd.txt19 reg=<0 0x18000000 0 0x1000>,
20 <0 0x18080000 0 0x8000>;
23 mediatek,offset = <0xf00 0x800 0xfd0 0xfd4 0xfd8>;
/linux/tools/perf/arch/powerpc/util/
H A Dbook3s_hv_exits.h10 {0x0, "RETURN_TO_HOST"}, \
11 {0x100, "SYSTEM_RESET"}, \
12 {0x200, "MACHINE_CHECK"}, \
13 {0x300, "DATA_STORAGE"}, \
14 {0x380, "DATA_SEGMENT"}, \
15 {0x400, "INST_STORAGE"}, \
16 {0x480, "INST_SEGMENT"}, \
17 {0x500, "EXTERNAL"}, \
18 {0x502, "EXTERNAL_HV"}, \
19 {0x600, "ALIGNMENT"}, \
[all …]
/linux/arch/powerpc/kvm/
H A Dtrace_book3s.h10 {0x100, "SYSTEM_RESET"}, \
11 {0x200, "MACHINE_CHECK"}, \
12 {0x300, "DATA_STORAGE"}, \
13 {0x380, "DATA_SEGMENT"}, \
14 {0x400, "INST_STORAGE"}, \
15 {0x480, "INST_SEGMENT"}, \
16 {0x500, "EXTERNAL"}, \
17 {0x502, "EXTERNAL_HV"}, \
18 {0x600, "ALIGNMENT"}, \
19 {0x700, "PROGRAM"}, \
[all …]
/linux/drivers/hwtracing/coresight/
H A Dcoresight-priv.h19 * Coresight management registers (0xf00-0xfcc)
20 * 0xfa0 - 0xfa4: Management registers in PFTv1.0
23 #define CORESIGHT_ITCTRL 0xf00
24 #define CORESIGHT_CLAIMSET 0xfa0
25 #define CORESIGHT_CLAIMCLR 0xfa
[all...]
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dnxp,lpc3220-usb-clk.yaml33 reg = <0xf00 0x100>;

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