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/linux/arch/arm64/boot/dts/freescale/
H A Dqoriq-fman3-0-1g-1.dtsi11 cell-index = <0x9>;
13 reg = <0x89000 0x1000>;
17 cell-index = <0x29>;
19 reg = <0xa9000 0x1000>;
25 reg = <0xe2000 0x1000>;
34 #size-cells = <0>;
36 reg = <0xe3000 0x1000>;
38 pcsphy1: ethernet-phy@0 {
39 reg = <0x0>;
/linux/arch/powerpc/boot/dts/fsl/
H A Dqoriq-fman3-0-10g-3.dtsi3 * QorIQ FMan v3 10g port #3 device tree stub [ controller @ offset 0x400000 ]
11 cell-index = <0x9>;
13 reg = <0x89000 0x1000>;
18 cell-index = <0x29>;
20 reg = <0xa9000 0x1000>;
27 reg = <0xe2000 0x1000>;
36 #size-cells = <0>;
38 reg = <0xe3000 0x1000>;
41 pcsphy1: ethernet-phy@0 {
42 reg = <0x0>;
H A Dqoriq-fman-1-1g-1.dtsi2 * QorIQ FMan 1g port #1 device tree stub [ controller @ offset 0x500000 ]
37 cell-index = <0x9>;
39 reg = <0x89000 0x1000>;
43 cell-index = <0x29>;
45 reg = <0xa9000 0x1000>;
51 reg = <0xe2000 0x1000>;
59 #size-cells = <0>;
61 reg = <0xe3120 0xee0>;
64 reg = <0x8>;
H A Dqoriq-fman-0-1g-1.dtsi2 * QorIQ FMan 1g port #1 device tree stub [ controller @ offset 0x400000 ]
37 cell-index = <0x9>;
39 reg = <0x89000 0x1000>;
43 cell-index = <0x29>;
45 reg = <0xa9000 0x1000>;
51 reg = <0xe2000 0x1000>;
59 #size-cells = <0>;
61 reg = <0xe3120 0xee0>;
64 reg = <0x8>;
H A Dqoriq-fman3-1-1g-1.dtsi2 * QorIQ FMan v3 1g port #1 device tree stub [ controller @ offset 0x500000 ]
37 cell-index = <0x9>;
39 reg = <0x89000 0x1000>;
43 cell-index = <0x29>;
45 reg = <0xa9000 0x1000>;
51 reg = <0xe2000 0x1000>;
67 #size-cells = <0>;
69 reg = <0xe3000 0x1000>;
72 pcsphy9: ethernet-phy@0 {
73 reg = <0x0>;
H A Dqoriq-fman3-0-1g-1.dtsi2 * QorIQ FMan v3 1g port #1 device tree stub [ controller @ offset 0x400000 ]
37 cell-index = <0x9>;
39 reg = <0x89000 0x1000>;
43 cell-index = <0x29>;
45 reg = <0xa9000 0x1000>;
51 reg = <0xe2000 0x1000>;
67 #size-cells = <0>;
69 reg = <0xe3000 0x1000>;
72 pcsphy1: ethernet-phy@0 {
73 reg = <0x0>;
H A Dqoriq-fman3-0-10g-1-best-effort.dtsi2 * QorIQ FMan v3 1g port #1 device tree stub [ controller @ offset 0x400000 ]
37 cell-index = <0x9>;
39 reg = <0x89000 0x1000>;
45 cell-index = <0x29>;
47 reg = <0xa9000 0x1000>;
55 reg = <0xe2000 0x1000>;
71 #size-cells = <0>;
73 reg = <0xe3000 0x1000>;
76 pcsphy1: ethernet-phy@0 {
77 reg = <0x0>;
H A Dp5020si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
52 interrupts = <25 2 0 0>;
57 /* controller at 0x200000 */
63 bus-range = <0x0 0xff>;
67 fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */
68 pcie@0 {
69 reg = <0 0 0 0 0>;
75 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
H A Dp3041si-post.dtsi37 alloc-ranges = <0 0 0x10 0>;
42 alloc-ranges = <0 0 0x10 0>;
47 alloc-ranges = <0 0 0x10 0>;
52 interrupts = <25 2 0 0>;
57 /* controller at 0x200000 */
63 bus-range = <0x0 0xff>;
67 fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */
68 pcie@0 {
69 reg = <0 0 0 0 0>;
75 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
H A Dp5040si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
52 interrupts = <25 2 0 0>;
57 /* controller at 0x200000 */
63 bus-range = <0x0 0xff>;
67 pcie@0 {
68 reg = <0 0 0 0 0>;
74 interrupt-map-mask = <0xf800 0 0 7>;
76 /* IDSEL 0x0 */
[all …]
H A Dp2041si-post.dtsi37 alloc-ranges = <0 0 0x10 0>;
42 alloc-ranges = <0 0 0x10 0>;
47 alloc-ranges = <0 0 0x10 0>;
52 interrupts = <25 2 0 0>;
57 /* controller at 0x200000 */
63 bus-range = <0x0 0xff>;
67 fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */
68 pcie@0 {
69 reg = <0 0 0 0 0>;
75 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
H A Dt1023si-post.dtsi39 alloc-ranges = <0 0 0x10000 0>;
44 alloc-ranges = <0 0 0x10000 0>;
49 alloc-ranges = <0 0 0x10000 0>;
56 interrupts = <25 2 0 0>;
64 bus-range = <0x0 0xff>;
65 interrupts = <20 2 0 0>;
67 pcie@0 {
68 reg = <0 0 0 0 0>;
73 interrupts = <20 2 0 0>;
74 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
H A Db4si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x200000 */
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
66 pcie@0 {
71 reg = <0 0 0 0 0>;
72 interrupts = <20 2 0 0>;
[all …]
H A Dp4080si-post.dtsi37 alloc-ranges = <0 0 0x10 0>;
42 alloc-ranges = <0 0 0x10 0>;
47 alloc-ranges = <0 0 0x10 0>;
52 interrupts = <25 2 0 0>;
57 /* controller at 0x200000 */
63 bus-range = <0x0 0xff>;
67 fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */
68 pcie@0 {
69 reg = <0 0 0 0 0>;
75 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
H A Dt2081si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
66 pcie@0 {
67 reg = <0 0 0 0 0>;
[all …]
H A Dt1040si-post.dtsi39 alloc-ranges = <0 0 0x10000 0>;
44 alloc-ranges = <0 0 0x10000 0>;
49 alloc-ranges = <0 0 0x10000 0>;
56 interrupts = <25 2 0 0>;
64 bus-range = <0x0 0xff>;
65 interrupts = <20 2 0 0>;
67 pcie@0 {
68 reg = <0 0 0 0 0>;
73 interrupts = <20 2 0 0>;
74 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
H A Dt4240si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
65 pcie@0 {
70 reg = <0 0 0 0 0>;
[all …]
/linux/Documentation/devicetree/bindings/soc/fsl/
H A Dfsl,rcpm.yaml85 reg = <0xe2000 0x1000>;
/linux/drivers/gpu/drm/i915/display/
H A Dintel_audio_regs.h11 #define G4X_AUD_CNTL_ST _MMIO(0x620B4)
16 #define G4X_HDMIW_HDMIEDID _MMIO(0x6210C)
18 #define _IBX_HDMIW_HDMIEDID_A 0xE2050
19 #define _IBX_HDMIW_HDMIEDID_B 0xE2150
22 #define _IBX_AUD_CNTL_ST_A 0xE20B4
23 #define _IBX_AUD_CNTL_ST_B 0xE21B4
29 #define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0)
31 #define IBX_ELD_VALID(port) REG_BIT(((port) - 1) * 4 + 0)
33 #define _CPT_HDMIW_HDMIEDID_A 0xE5050
34 #define _CPT_HDMIW_HDMIEDID_B 0xE5150
[all …]
/linux/drivers/mtd/nand/raw/
H A Ddiskonchip.c37 #define CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS 0
43 0xfffc8000, 0xfffca000, 0xfffcc000, 0xfffce000,
44 0xfffd0000, 0xfffd2000, 0xfffd4000, 0xfffd6000,
45 0xfffd8000, 0xfffda000, 0xfffdc000, 0xfffde000,
46 0xfffe0000, 0xfffe2000, 0xfffe4000, 0xfffe6000,
47 0xfffe8000, 0xfffea000, 0xfffec000, 0xfffee000,
49 0xc8000, 0xca000, 0xcc000, 0xce000,
50 0xd0000, 0xd2000, 0xd4000, 0xd6000,
51 0xd8000, 0xda000, 0xdc000, 0xde000,
52 0xe0000, 0xe2000, 0xe4000, 0xe6000,
[all …]
/linux/drivers/net/ethernet/xircom/
H A Dxirc2ps_cs.c94 #define MANFID_COMPAQ 0x0138
95 #define MANFID_COMPAQ2 0x0183 /* is this correct? */
108 #define XIRCREG_CR 0 /* Command register (wr) */
110 TransmitPacket = 0x01,
111 SoftReset = 0x02,
112 EnableIntr = 0x04,
113 ForceIntr = 0x08,
114 ClearTxFIFO = 0x10,
115 ClearRxOvrun = 0x20,
116 RestartTx = 0x40
[all …]
/linux/drivers/clk/qcom/
H A Dgcc-glymur.c133 .offset = 0x0,
136 .enable_reg = 0x62040,
137 .enable_mask = BIT(0),
150 { 0x1, 2 },
155 .offset = 0x0,
172 .offset = 0x1000,
175 .enable_reg = 0x62040,
189 .offset = 0xe000,
192 .enable_reg = 0x62040,
206 { 0x1, 2 },
[all …]
/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_dump.h22 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
23 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
24 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
25 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
45 #define BNX2X_DUMP_VERSION 0x61111111
65 static const u32 page_vals_e2[] = {0, 128};
68 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
74 static const u32 page_vals_e3[] = {0, 128};
77 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
81 { 0x2000, 1, 0x1f, 0xfff},
[all …]
H A Dbnx2x_reg.h26 #define ATC_ATC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
27 #define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS (0x1<<2)
28 #define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU (0x1<<5)
29 #define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT (0x1<<3)
30 #define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR (0x1<<4)
31 #define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND (0x1<<1)
33 #define ATC_REG_ATC_INIT_ARRAY 0x1100b8
35 #define ATC_REG_ATC_INIT_DONE 0x1100bc
36 /* [RC 6] Interrupt register #0 read clear */
37 #define ATC_REG_ATC_INT_STS_CLR 0x1101c0
[all …]