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/linux/drivers/gpu/drm/amd/amdgpu/
H A Dimu_v11_0.c101 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_ADDR, 0); in imu_v11_0_load_microcode()
103 for (i = 0; i < fw_size; i++) in imu_v11_0_load_microcode()
104 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_DATA, le32_to_cpup(fw_data++)); in imu_v11_0_load_microcode()
106 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_ADDR, adev->gfx.imu_fw_version); in imu_v11_0_load_microcode()
113 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_ADDR, 0); in imu_v11_0_load_microcode()
115 for (i = 0; i < fw_size; i++) in imu_v11_0_load_microcode()
116 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_DATA, le32_to_cpup(fw_data++)); in imu_v11_0_load_microcode()
118 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_ADDR, adev->gfx.imu_fw_version); in imu_v11_0_load_microcode()
120 return 0; in imu_v11_0_load_microcode()
125 int i, imu_reg_val = 0; in imu_v11_0_wait_for_reset_status()
[all …]
H A Dimu_v11_0_3.c31 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_IO_RD_COMBINE_FLUSH, 0x00055555, 0xe0000000),
32 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_IO_WR_COMBINE_FLUSH, 0x00055555, 0xe0000000),
33 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_DRAM_COMBINE_FLUSH, 0x00555555, 0xe0000000),
34 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_MISC2, 0x00001ffe, 0xe0000000),
35 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_CREDITS, 0x003f3fff, 0xe0000000),
36 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_TAG_RESERVE1, 0x00000000, 0xe0000000),
37 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCC_RESERVE0, 0x00041000, 0xe0000000),
38 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCC_RESERVE1, 0x00000000, 0xe0000000),
39 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCD_RESERVE0, 0x00040000, 0xe0000000),
40 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCD_RESERVE1, 0x00000000, 0xe0000000),
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dcyrus_p5020.dts30 size = <0 0x1000000>;
31 alignment = <0 0x1000000>;
34 size = <0 0x400000>;
35 alignment = <0 0x400000>;
38 size = <0 0x2000000>;
39 alignment = <0 0x2000000>;
44 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
48 ranges = <0x0 0xf 0xf4000000 0x200000>;
52 ranges = <0x0 0xf 0xf4200000 0x200000>;
56 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
[all …]
H A Dmpc8572ds_36b.dts19 reg = <0xf 0xffe05000 0 0x1000>;
21 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
22 0x1 0x0 0xf 0xe0000000 0x08000000
23 0x2 0x0 0xf 0xffa00000 0x00040000
24 0x3 0x0 0xf 0xffdf0000 0x00008000
25 0x4 0x0 0xf 0xffa40000 0x00040000
26 0x5 0x0 0xf 0xffa80000 0x00040000
27 0x6 0x0 0xf 0xffac0000 0x00040000>;
31 ranges = <0x0 0xf 0xffe00000 0x100000>;
35 reg = <0xf 0xffe08000 0 0x1000>;
[all …]
H A Dp1022ds_36b.dts45 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
46 0x1 0x0 0xf 0xe0000000 0x08000000
47 0x2 0x0 0xf 0xff800000 0x00040000
48 0x3 0x0 0xf 0xffdf0000 0x00008000>;
49 reg = <0xf 0xffe05000 0 0x1000>;
53 ranges = <0x0 0xf 0xffe00000 0x100000>;
57 ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
58 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
59 reg = <0xf 0xffe09000 0 0x1000>;
60 pcie@0 {
[all …]
H A Dp1022ds_32b.dts45 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
46 0x1 0x0 0x0 0xe0000000 0x08000000
47 0x2 0x0 0x0 0xff800000 0x00040000
48 0x3 0x0 0x0 0xffdf0000 0x00008000>;
49 reg = <0x0 0xffe05000 0 0x1000>;
53 ranges = <0x0 0x0 0xffe00000 0x100000>;
57 ranges = <0x2000000 0x0 0xe0000000 0 0xa0000000 0x0 0x20000000
58 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
59 reg = <0x0 0xffe09000 0 0x1000>;
60 pcie@0 {
[all …]
H A Dt208xrdb.dtsi48 size = <0 0x1000000>;
49 alignment = <0 0x1000000>;
52 size = <0 0x400000>;
53 alignment = <0 0x400000>;
56 size = <0 0x2000000>;
57 alignment = <0 0x2000000>;
62 reg = <0xf 0xfe124000 0 0x2000>;
63 ranges = <0 0 0xf 0xe8000000 0x08000000
64 2 0 0xf 0xff800000 0x00010000
65 3 0 0xf 0xffdf0000 0x00008000>;
[all …]
H A Dkmcent2.dts27 size = <0 0x1000000>;
28 alignment = <0 0x1000000>;
31 size = <0 0x400000>;
32 alignment = <0 0x400000>;
35 size = <0 0x2000000>;
36 alignment = <0 0x2000000>;
41 reg = <0xf 0xfe124000 0 0x2000>;
42 ranges = <0 0 0xf 0xe8000000 0x04000000
43 1 0 0xf 0xfa000000 0x00010000
44 2 0 0xf 0xfb000000 0x00010000
[all …]
H A Dt104xd4rdb.dtsi42 size = <0 0x1000000>;
43 alignment = <0 0x1000000>;
46 size = <0 0x400000>;
47 alignment = <0 0x400000>;
50 size = <0 0x2000000>;
51 alignment = <0 0x2000000>;
56 reg = <0xf 0xfe124000 0 0x2000>;
57 ranges = <0 0 0xf 0xe8000000 0x08000000
58 2 0 0xf 0xff800000 0x00010000
59 3 0 0xf 0xffdf0000 0x00008000>;
[all …]
H A Dt104xrdb.dtsi48 size = <0 0x1000000>;
49 alignment = <0 0x1000000>;
52 size = <0 0x400000>;
53 alignment = <0 0x400000>;
56 size = <0 0x2000000>;
57 alignment = <0 0x2000000>;
62 reg = <0xf 0xfe124000 0 0x2000>;
63 ranges = <0 0 0xf 0xe8000000 0x08000000
64 2 0 0xf 0xff800000 0x00010000
65 3 0 0xf 0xffdf0000 0x00008000>;
[all …]
H A Dt208xqds.dtsi48 size = <0 0x1000000>;
49 alignment = <0 0x1000000>;
52 size = <0 0x400000>;
53 alignment = <0 0x400000>;
56 size = <0 0x2000000>;
57 alignment = <0 0x2000000>;
62 reg = <0xf 0xfe124000 0 0x2000>;
63 ranges = <0 0 0xf 0xe8000000 0x08000000
64 2 0 0xf 0xff800000 0x00010000
65 3 0 0xf 0xffdf0000 0x00008000>;
[all …]
H A Dp1022rdk.dts50 ranges = <0x0 0x0 0xffe00000 0x100000>;
55 reg = <0x1a>;
61 reg = <0x68>;
65 reg = <0x4c>;
69 reg = <0x21>;
73 reg = <0x24>;
77 reg = <0x26>;
81 reg = <0x29>;
86 flash@0 {
90 reg = <0>;
[all …]
H A Dp1025rdb_32b.dts45 reg = <0 0xffe05000 0 0x1000>;
48 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
49 0x1 0x0 0x0 0xff800000 0x00040000>;
53 ranges = <0x0 0x0 0xffe00000 0x100000>;
57 ranges = <0x2000000 0x0 0xe0000000 0 0xe0000000 0x0 0x20000000
58 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
59 reg = <0 0xffe09000 0 0x1000>;
60 pcie@0 {
61 ranges = <0x2000000 0x0 0xe0000000
62 0x2000000 0x0 0xe0000000
[all …]
H A Dt4240rdb.dts56 reg = <0xf 0xfe124000 0 0x2000>;
57 ranges = <0 0 0xf 0xe8000000 0x08000000
58 2 0 0xf 0xff800000 0x00010000
59 3 0 0xf 0xffdf0000 0x00008000>;
61 nor@0,0 {
65 reg = <0x0 0x0 0x8000000>;
71 nand@2,0 {
75 reg = <0x2 0x0 0x10000>;
89 size = <0 0x1000000>;
90 alignment = <0 0x1000000>;
[all …]
H A Dp3041ds.dts68 size = <0 0x1000000>;
69 alignment = <0 0x1000000>;
72 size = <0 0x400000>;
73 alignment = <0 0x400000>;
76 size = <0 0x2000000>;
77 alignment = <0 0x2000000>;
82 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
86 ranges = <0x0 0xf 0xf4000000 0x200000>;
90 ranges = <0x0 0xf 0xf4200000 0x200000>;
94 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
[all …]
H A Dp5020ds.dts68 size = <0 0x1000000>;
69 alignment = <0 0x1000000>;
72 size = <0 0x400000>;
73 alignment = <0 0x400000>;
76 size = <0 0x2000000>;
77 alignment = <0 0x2000000>;
82 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
86 ranges = <0x0 0xf 0xf4000000 0x200000>;
90 ranges = <0x0 0xf 0xf4200000 0x200000>;
94 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
[all …]
H A Dt1023rdb.dts50 size = <0 0x1000000>;
51 alignment = <0 0x1000000>;
55 size = <0 0x400000>;
56 alignment = <0 0x400000>;
60 size = <0 0x2000000>;
61 alignment = <0 0x2000000>;
66 reg = <0xf 0xfe124000 0 0x2000>;
67 ranges = <0 0 0xf 0xe8000000 0x08000000
68 1 0 0xf 0xff800000 0x00010000>;
70 nor@0,0 {
[all …]
H A Dp1024rdb_36b.dts45 reg = <0xf 0xffe05000 0 0x1000>;
46 ranges = <0x0 0x0 0xf 0xef000000 0x01000000
47 0x1 0x0 0xf 0xff800000 0x00040000>;
51 ranges = <0x0 0xf 0xffe00000 0x100000>;
55 reg = <0xf 0xffe09000 0 0x1000>;
56 ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
57 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
58 pcie@0 {
59 ranges = <0x2000000 0x0 0xe0000000
60 0x2000000 0x0 0xe0000000
[all …]
H A Dp1024rdb_32b.dts45 reg = <0x0 0xffe05000 0 0x1000>;
46 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
47 0x1 0x0 0x0 0xff800000 0x00040000>;
51 ranges = <0x0 0x0 0xffe00000 0x100000>;
55 reg = <0x0 0xffe09000 0 0x1000>;
56 ranges = <0x2000000 0x0 0xe0000000 0x0 0xa0000000 0x0 0x20000000
57 0x1000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x10000>;
58 pcie@0 {
59 ranges = <0x2000000 0x0 0xe0000000
60 0x2000000 0x0 0xe0000000
[all …]
H A Dt104xqds.dtsi74 size = <0 0x1000000>;
75 alignment = <0 0x1000000>;
78 size = <0 0x400000>;
79 alignment = <0 0x400000>;
82 size = <0 0x2000000>;
83 alignment = <0 0x2000000>;
88 reg = <0xf 0xfe124000 0 0x2000>;
89 ranges = <0 0 0xf 0xe8000000 0x08000000
90 2 0 0xf 0xff800000 0x00010000
91 3 0 0xf 0xffdf0000 0x00008000>;
[all …]
H A Dp2020rdb-pc_36b.dts46 reg = <0xf 0xffe05000 0 0x1000>;
49 ranges = <0x0 0x0 0xf 0xef000000 0x01000000
50 0x1 0x0 0xf 0xff800000 0x00040000
51 0x2 0x0 0xf 0xffb00000 0x00020000
52 0x3 0x0 0xf 0xffa00000 0x00020000>;
56 ranges = <0x0 0xf 0xffe00000 0x100000>;
60 reg = <0xf 0xffe08000 0 0x1000>;
65 reg = <0xf 0xffe09000 0 0x1000>;
66 ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
67 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
[all …]
H A Dp2020rdb-pc_32b.dts46 reg = <0 0xffe05000 0 0x1000>;
49 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
50 0x1 0x0 0x0 0xff800000 0x00040000
51 0x2 0x0 0x0 0xffb00000 0x00020000
52 0x3 0x0 0x0 0xffa00000 0x00020000>;
56 ranges = <0x0 0x0 0xffe00000 0x100000>;
60 reg = <0 0xffe08000 0 0x1000>;
65 reg = <0 0xffe09000 0 0x1000>;
66 ranges = <0x2000000 0x0 0xe0000000 0 0xa0000000 0x0 0x20000000
67 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
[all …]
H A Dp1020mbg-pc_32b.dts45 reg = <0x0 0xffe05000 0x0 0x1000>;
48 ranges = <0x0 0x0 0x0 0xec000000 0x04000000
49 0x1 0x0 0x0 0xffa00000 0x00040000
50 0x2 0x0 0x0 0xffb00000 0x00020000>;
54 ranges = <0x0 0x0 0xffe00000 0x100000>;
58 reg = <0x0 0xffe09000 0x0 0x1000>;
59 ranges = <0x2000000 0x0 0xe0000000 0x0 0xa0000000 0x0 0x20000000
60 0x1000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x10000>;
61 pcie@0 {
62 ranges = <0x2000000 0x0 0xe0000000
[all …]
H A Dp1020utm-pc_32b.dts45 reg = <0x0 0xffe05000 0x0 0x1000>;
48 ranges = <0x0 0x0 0x0 0xec000000 0x02000000
49 0x1 0x0 0x0 0xffa00000 0x00040000
50 0x2 0x0 0x0 0xffb00000 0x00020000>;
54 ranges = <0x0 0x0 0xffe00000 0x100000>;
58 reg = <0x0 0xffe09000 0x0 0x1000>;
59 ranges = <0x2000000 0x0 0xe0000000 0x0 0xa0000000 0x0 0x20000000
60 0x1000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x10000>;
61 pcie@0 {
62 ranges = <0x2000000 0x0 0xe0000000
[all …]
H A Dp1020utm-pc_36b.dts45 reg = <0xf 0xffe05000 0x0 0x1000>;
48 ranges = <0x0 0x0 0xf 0xec000000 0x02000000
49 0x1 0x0 0xf 0xffa00000 0x00040000
50 0x2 0x0 0xf 0xffb00000 0x00020000>;
54 ranges = <0x0 0xf 0xffe00000 0x100000>;
58 reg = <0xf 0xffe09000 0x0 0x1000>;
59 ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
60 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
61 pcie@0 {
62 ranges = <0x2000000 0x0 0xe0000000
[all …]

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