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/freebsd/sys/contrib/device-tree/Bindings/soc/qcom/
H A Dqcom,rpmh-rsc.yaml78 enum: [ 0, 1, 2, 3 ]
97 - const: drv-0
115 '^regulators(-[0-9])?$':
133 // For a TCS whose RSC base address is 0x179C0000 and is at a DRV id of
134 // 2, the register offsets for DRV2 start at 0D00, the register
136 // DRV0: 0x179C0000
137 // DRV2: 0x179C0000 + 0x10000 = 0x179D0000
138 // DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000
139 // TCS-OFFSET: 0xD00
145 reg = <0x179c0000 0x10000>,
[all …]
H A Drpmh-rsc.txt52 "drv-0", "drv-1", "drv-2" etc and "tcs-offset". The
91 For a TCS whose RSC base address is is 0x179C0000 and is at a DRV id of 2, the
92 register offsets for DRV2 start at 0D00, the register calculations are like
94 DRV0: 0x179C0000
95 DRV2: 0x179C0000 + 0x10000 = 0x179D0000
96 DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000
97 TCS-OFFSET: 0xD00
102 reg = <0x179c0000 0x10000>,
103 <0x179d0000 0x10000>,
104 <0x179e0000 0x10000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/exynos/
H A Dexynos7.dtsi44 #clock-cells = <0>;
49 #size-cells = <0>;
51 cpu_atlas0: cpu@0 {
54 reg = <0x0>;
56 i-cache-size = <0xc000>;
59 d-cache-size = <0x8000>;
68 reg = <0x1>;
70 i-cache-size = <0xc000>;
73 d-cache-size = <0x8000>;
82 reg = <0x
[all...]
/freebsd/sys/contrib/device-tree/Bindings/timer/
H A Dralink,cevt-systick.yaml33 reg = <0xd00 0x10>;
/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A D8xxx_gpio.txt48 reg = <0xc00 0x100>;
50 interrupts = <74 0x8>;
59 reg = <0xd00 0x100>;
61 interrupts = <75 0x8>;
67 funkyfpga@0 {
/freebsd/sys/dev/xdma/controller/
H A Dpl330.h35 #define DSR 0x000 /* DMA Manager Status */
36 #define DPC 0x004 /* DMA Program Counter */
37 #define INTEN 0x020 /* Interrupt Enable */
38 #define INT_EVENT_RIS 0x024 /* Event-Interrupt Raw Status */
39 #define INTMIS 0x028 /* Interrupt Status */
40 #define INTCLR 0x02C /* Interrupt Clear */
41 #define FSRD 0x030 /* Fault Status DMA Manager */
42 #define FSRC 0x034 /* Fault Status DMA Channel */
43 #define FTRD 0x038 /* Fault Type DMA Manager */
44 #define FTR(n) (0x040 + 0x04 * (n)) /* Fault type for DMA channel n */
[all …]
/freebsd/sys/contrib/dev/rtw88/
H A Drtw8822b.h13 u8 res4[4]; /* 0xd0 */
15 u8 res5[0x1e];
17 u8 serial[0x0b]; /* 0xf5 */
18 u8 vid; /* 0x100 */
22 u8 mac_addr[ETH_ALEN]; /* 0x107 */
24 u8 vendor_name[0x07];
26 u8 device_name[0x14];
27 u8 res11[0xcf];
28 u8 package_type; /* 0x1fb */
29 u8 res12[0x4];
[all …]
H A Drtw8821c.h13 u8 res4[4]; /* 0xd0 */
15 u8 res5[0x1e];
17 u8 serial[0x0b]; /* 0xf5 */
18 u8 vid; /* 0x100 */
22 u8 mac_addr[ETH_ALEN]; /* 0x107 */
24 u8 vendor_name[0x07];
26 u8 device_name[0x14];
27 u8 res11[0xcf];
28 u8 package_type; /* 0x1f
[all...]
/freebsd/sys/dev/bhnd/cores/pcie2/
H A Dbhnd_pcie2_reg.h31 #define BHND_PCIE2_DMA64_TRANSLATION 0x8000000000000000 /**< PCIe-Gen2 DMA64 address translation */
32 #define BHND_PCIE2_DMA64_MASK 0xc000000000000000 /**< PCIe-Gen2 DMA64 translation mask */
38 #define BHND_PCIE2_CLK_CONTROL 0x000
40 #define BHND_PCIE2_RC_PM_CONTROL 0x004
41 #define BHND_PCIE2_RC_PM_STATUS 0x008
42 #define BHND_PCIE2_EP_PM_CONTROL 0x00C
43 #define BHND_PCIE2_EP_PM_STATUS 0x010
44 #define BHND_PCIE2_EP_LTR_CONTROL 0x014
45 #define BHND_PCIE2_EP_LTR_STATUS 0x018
46 #define BHND_PCIE2_EP_OBFF_STATUS 0x01C
[all …]
/freebsd/sys/contrib/device-tree/src/mips/ralink/
H A Dmt7628a.dtsi10 #size-cells = <0>;
12 cpu@0 {
15 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10000000 0x200000>;
34 ranges = <0x0 0x10000000 0x1FFFFF>;
39 sysc: system-controller@0 {
41 reg = <0x0 0x60>;
46 reg = <0x60 0x8>;
48 #size-cells = <0>;
[all …]
H A Dmt7621.dtsi15 #size-cells = <0>;
17 cpu@0 {
19 reg = <0>;
33 #address-cells = <0>;
149 reg = <0x1e000000 0x100000>;
150 ranges = <0x0 0x1e000000 0x0fffff>;
155 sysc: syscon@0 {
157 reg = <0x0 0x100>;
171 reg = <0x100 0x100>;
177 reg = <0x600 0x100>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/qcom/
H A Dqcom-sdx65.dtsi20 qcom,msm-id = <458 0x10000>, <483 0x10000>, <509 0x10000>;
25 reg = <0 0>;
33 #clock-cells = <0>;
40 #clock-cells = <0>;
46 #clock-cells = <0>;
52 #size-cells = <0>;
54 cpu0: cpu@0 {
57 reg = <0x0>;
115 reg = <0x8fcad000 0x40000>;
120 reg = <0x8fcfd000 0x1000>;
[all …]
/freebsd/sys/arm64/include/
H A Dcpu.h59 /* Extract CPU affinity levels 0-3 */
60 #define CPU_AFF0(mpidr) (u_int)(((mpidr) >> 0) & 0xff)
61 #define CPU_AFF1(mpidr) (u_int)(((mpidr) >> 8) & 0xff)
62 #define CPU_AFF2(mpidr) (u_int)(((mpidr) >> 16) & 0xff)
63 #define CPU_AFF3(mpidr) (u_int)(((mpidr) >> 32) & 0xff)
64 #define CPU_AFF0_MASK 0xffUL
65 #define CPU_AFF1_MASK 0xff00UL
66 #define CPU_AFF2_MASK 0xff0000UL
67 #define CPU_AFF3_MASK 0xff00000000UL
73 #define CPU_IMPL_ARM 0x41
[all …]
/freebsd/sys/dev/rtwn/rtl8192c/pci/
H A Dr92ce_priv.h31 { 0x420, 0x80 }, { 0x423, 0x00 }, { 0x430, 0x00 }, { 0x431, 0x00 },
32 { 0x432, 0x00 }, { 0x433, 0x01 }, { 0x434, 0x04 }, { 0x435, 0x05 },
33 { 0x436, 0x06 }, { 0x437, 0x07 }, { 0x438, 0x00 }, { 0x439, 0x00 },
34 { 0x43a, 0x00 }, { 0x43b, 0x01 }, { 0x43c, 0x04 }, { 0x43d, 0x05 },
35 { 0x43e, 0x06 }, { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 },
36 { 0x442, 0x00 }, { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f },
37 { 0x447, 0x00 }, { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 },
38 { 0x45b, 0xb9 }, { 0x460, 0x88 }, { 0x461, 0x88 }, { 0x462, 0x06 },
39 { 0x463, 0x03 }, { 0x4c8, 0x04 }, { 0x4c9, 0x08 }, { 0x4cc, 0x02 },
40 { 0x4cd, 0x28 }, { 0x4ce, 0x01 }, { 0x500, 0x26 }, { 0x501, 0xa2 },
[all …]
/freebsd/sys/contrib/device-tree/src/arm/actions/
H A Dowl-s500.dtsi28 #size-cells = <0>;
30 cpu0: cpu@0 {
33 reg = <0x0>;
40 reg = <0x1>;
47 reg = <0x2>;
55 reg = <0x3>;
73 #clock-cells = <0>;
79 #clock-cells = <0>;
90 reg = <0xb0020000 0x100>;
95 reg = <0xb0020200 0x100>;
[all …]
/freebsd/sys/contrib/dev/iwlwifi/
H A Diwl-fh.h22 #define FH_MEM_LOWER_BOUND (0x1000)
23 #define FH_MEM_UPPER_BOUND (0x2000)
24 #define FH_MEM_LOWER_BOUND_GEN2 (0xa06000)
25 #define FH_MEM_UPPER_BOUND_GEN2 (0xa08000)
42 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
44 #define FH_KW_MEM_ADDR_REG (FH_MEM_LOWER_BOUND + 0x97C)
52 * (see struct iwl_tfd_frame). These 16 pointer registers are offset by 0x04
54 * aligned (address bits 0-7 must be 0).
59 * 27-0
[all...]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dmpc8349emitx.dts27 #size-cells = <0>;
29 PowerPC,8349@0 {
31 reg = <0x0>;
36 timebase-frequency = <0>; // from bootloader
37 bus-frequency = <0>; // from bootloader
38 clock-frequency = <0>; // from bootloader
44 reg = <0x00000000 0x10000000>;
52 ranges = <0x0 0xe0000000 0x00100000>;
53 reg = <0xe0000000 0x00000200>;
54 bus-frequency = <0>; // from bootloader
[all …]
H A Dmpc8377_wlan.dts28 #size-cells = <0>;
30 PowerPC,8377@0 {
32 reg = <0x0>;
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
45 reg = <0x00000000 0x20000000>; // 512MB at 0
52 reg = <0xe0005000 0x1000>;
53 interrupts = <77 0x8>;
55 ranges = <0x0 0x0 0xfc000000 0x04000000>;
[all …]
H A Dmpc8379_rdb.dts25 #size-cells = <0>;
27 PowerPC,8379@0 {
29 reg = <0x0>;
34 timebase-frequency = <0>;
35 bus-frequency = <0>;
36 clock-frequency = <0>;
42 reg = <0x00000000 0x10000000>; // 256MB at 0
49 reg = <0xe0005000 0x1000>;
50 interrupts = <77 0x8>;
56 ranges = <0x0 0x0 0xfe000000 0x00800000
[all …]
H A Dmpc8377_rdb.dts27 #size-cells = <0>;
29 PowerPC,8377@0 {
31 reg = <0x0>;
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
44 reg = <0x00000000 0x10000000>; // 256MB at 0
51 reg = <0xe0005000 0x1000>;
52 interrupts = <77 0x8>;
58 ranges = <0x0 0x0 0xfe000000 0x00800000
[all …]
H A Dmpc8378_rdb.dts27 #size-cells = <0>;
29 PowerPC,8378@0 {
31 reg = <0x0>;
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
44 reg = <0x00000000 0x10000000>; // 256MB at 0
51 reg = <0xe0005000 0x1000>;
52 interrupts = <77 0x8>;
58 ranges = <0x0 0x0 0xfe000000 0x00800000
[all …]
/freebsd/sys/dev/rtwn/rtl8188e/
H A Dr88e_priv.h39 { 0x026, 0x41 }, { 0x027, 0x35 }, { 0x040, 0x00 }, { 0x428, 0x0a },
40 { 0x429, 0x10 }, { 0x430, 0x00 }, { 0x431, 0x01 }, { 0x432, 0x02 },
41 { 0x433, 0x04 }, { 0x434, 0x05 }, { 0x435, 0x06 }, { 0x436, 0x07 },
42 { 0x437, 0x08 }, { 0x438, 0x00 }, { 0x439, 0x00 }, { 0x43a, 0x01 },
43 { 0x43b, 0x02 }, { 0x43c, 0x04 }, { 0x43d, 0x05 }, { 0x43e, 0x06 },
44 { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 }, { 0x442, 0x00 },
45 { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f }, { 0x447, 0x00 },
46 { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 }, { 0x45b, 0xb9 },
47 { 0x460, 0x66 }, { 0x461, 0x66 }, { 0x480, 0x08 }, { 0x4c8, 0xff },
48 { 0x4c9, 0x08 }, { 0x4cc, 0xff }, { 0x4cd, 0xff }, { 0x4ce, 0x01 },
[all …]
/freebsd/sys/dev/dpaa2/
H A Ddpaa2_swp.h44 #define DPAA2_SWP_VALID_BIT ((uint32_t) 0x80)
67 #define DPAA2_SWP_REV_4000 0x04000000
68 #define DPAA2_SWP_REV_4100 0x04010000
69 #define DPAA2_SWP_REV_4101 0x04010001
70 #define DPAA2_SWP_REV_5000 0x05000000
72 #define DPAA2_SWP_REV_MASK 0xFFFF0000
75 #define DPAA2_SWP_CINH_CR 0x600 /* Management Command reg.*/
76 #define DPAA2_SWP_CINH_EQCR_PI 0x800 /* Enqueue Ring, Producer Index */
77 #define DPAA2_SWP_CINH_EQCR_CI 0x840 /* Enqueue Ring, Consumer Index */
78 #define DPAA2_SWP_CINH_CR_RT 0x900 /* CR Read Trigger */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap54xx-clocks.dtsi9 #clock-cells = <0>;
16 #clock-cells = <0>;
21 reg = <0x0108>;
25 #clock-cells = <0>;
32 #clock-cells = <0>;
39 #clock-cells = <0>;
44 reg = <0x0108>;
48 #clock-cells = <0>;
55 #clock-cells = <0>;
62 #clock-cells = <0>;
[all …]
/freebsd/sys/dev/rtwn/rtl8192c/usb/
H A Dr92cu_priv.h29 { 0x420, 0x80 }, { 0x423, 0x00 }, { 0x430, 0x00 }, { 0x431, 0x00 },
30 { 0x432, 0x00 }, { 0x433, 0x01 }, { 0x434, 0x04 }, { 0x435, 0x05 },
31 { 0x436, 0x06 }, { 0x437, 0x07 }, { 0x438, 0x00 }, { 0x439, 0x00 },
32 { 0x43a, 0x00 }, { 0x43b, 0x01 }, { 0x43c, 0x04 }, { 0x43d, 0x05 },
33 { 0x43e, 0x06 }, { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 },
34 { 0x442, 0x00 }, { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f },
35 { 0x447, 0x00 }, { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 },
36 { 0x45b, 0xb9 }, { 0x460, 0x66 }, { 0x461, 0x66 }, { 0x462, 0x08 },
37 { 0x463, 0x03 }, { 0x4c8, 0xff }, { 0x4c9, 0x08 }, { 0x4cc, 0xff },
38 { 0x4cd, 0xff }, { 0x4ce, 0x01 }, { 0x500, 0x26 }, { 0x501, 0xa2 },
[all …]

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