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/linux/fs/jffs2/
H A Dxattr.c32 * is_xattr_datum_unchecked(c, xd)
34 * unchecked, it returns 0.
35 * unload_xattr_datum(c, xd)
41 * do_verify_xattr_datum(c, xd)
45 * 0 will be returned, if success. An negative return value means recoverable error, and
48 * do_load_xattr_datum(c, xd)
51 * load_xattr_datum(c, xd)
53 * If xd need to call do_verify_xattr_datum() at first, it's called before calling
55 * save_xattr_datum(c, xd)
56 * is used to write xdatum to medium. xd->version will be incremented.
[all …]
/linux/arch/powerpc/sysdev/xive/
H A Dcommon.c43 #define DBG_VERBOSE(fmt...) do { } while(0)
92 static bool xive_is_store_eoi(struct xive_irq_data *xd) in xive_is_store_eoi() argument
94 return xd->flags & XIVE_IRQ_FLAG_STORE_EOI && xive_store_eoi; in xive_is_store_eoi()
99 * or 0 if there is no new entry.
108 return 0; in xive_read_eq()
113 return 0; in xive_read_eq()
121 if (q->idx == 0) in xive_read_eq()
125 return cur & 0x7fffffff; in xive_read_eq()
135 * (0xff if none) and return what was found (0 if none).
153 u32 irq = 0; in xive_scan_interrupts()
[all …]
/linux/drivers/net/thunderbolt/
H A Dmain.c36 #define TBNET_E2E BIT(0)
49 #define TBNET_L0_PORT_NUM(route) ((route) & GENMASK(5, 0))
60 * supported then @frame_id is filled, otherwise it stays %0.
92 #define TBIP_HDR_LENGTH_MASK GENMASK(5, 0)
151 * @xd: XDomain the service belongs to
182 struct tb_xdomain *xd; member
206 UUID_INIT(0xc66189ca, 0x1cce, 0x4195,
207 0xbd, 0xb8, 0x49, 0x59, 0x2e, 0x5f, 0x5a, 0x4f);
211 UUID_INIT(0x798f589e, 0x3616, 0x8a47,
212 0x97, 0xc6, 0x56, 0x64, 0xa9, 0x20, 0xc8, 0xdd);
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_3_0_1_sh_mask.h29 …RDCLI0__VIRT_CHAN__SHIFT 0x0
30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
31 …RDCLI0__URG_HIGH__SHIFT 0x4
32 …RDCLI0__URG_LOW__SHIFT 0x8
33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
34 …RDCLI0__MAX_BW__SHIFT 0xd
35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
36 …DCLI0__MIN_BW__SHIFT 0x16
37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
38 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
H A Dmmhub_3_0_0_sh_mask.h29 …RDCLI0__VIRT_CHAN__SHIFT 0x0
30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
31 …RDCLI0__URG_HIGH__SHIFT 0x4
32 …RDCLI0__URG_LOW__SHIFT 0x8
33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
34 …RDCLI0__MAX_BW__SHIFT 0xd
35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
36 …DCLI0__MIN_BW__SHIFT 0x16
37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
38 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
H A Dmmhub_3_0_2_sh_mask.h29 …RDCLI0__VIRT_CHAN__SHIFT 0x0
30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
31 …RDCLI0__URG_HIGH__SHIFT 0x4
32 …RDCLI0__URG_LOW__SHIFT 0x8
33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
34 …RDCLI0__MAX_BW__SHIFT 0xd
35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
36 …DCLI0__MIN_BW__SHIFT 0x16
37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
38 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
H A Dmmhub_4_1_0_sh_mask.h29 …RDCLI0__VIRT_CHAN__SHIFT 0x0
30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
31 …RDCLI0__URG_HIGH__SHIFT 0x4
32 …RDCLI0__URG_LOW__SHIFT 0x8
33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
34 …RDCLI0__MAX_BW__SHIFT 0xd
35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
36 …DCLI0__MIN_BW__SHIFT 0x16
37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
38 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
H A Dmmhub_3_3_0_sh_mask.h29 …RDCLI0__VIRT_CHAN__SHIFT 0x0
30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
31 …RDCLI0__URG_HIGH__SHIFT 0x4
32 …RDCLI0__URG_LOW__SHIFT 0x8
33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
34 …RDCLI0__MAX_BW__SHIFT 0xd
35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
36 …DCLI0__MIN_BW__SHIFT 0x16
37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
38 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
H A Dmmhub_2_3_0_sh_mask.h27 …RDCLI0__VIRT_CHAN__SHIFT 0x0
28 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
29 …RDCLI0__URG_HIGH__SHIFT 0x4
30 …RDCLI0__URG_LOW__SHIFT 0x8
31 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
32 …RDCLI0__MAX_BW__SHIFT 0xd
33 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
34 …DCLI0__MIN_BW__SHIFT 0x16
35 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
36 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
H A Dmmhub_1_8_0_sh_mask.h29 …RDCLI0__VIRT_CHAN__SHIFT 0x0
30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
31 …RDCLI0__URG_HIGH__SHIFT 0x4
32 …RDCLI0__URG_LOW__SHIFT 0x8
33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
34 …RDCLI0__MAX_BW__SHIFT 0xd
35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
36 …DCLI0__MIN_BW__SHIFT 0x16
37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
38 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
/linux/include/linux/
H A Dthunderbolt.h112 TB_PROPERTY_TYPE_UNKNOWN = 0x00,
113 TB_PROPERTY_TYPE_DIRECTORY = 0x44,
114 TB_PROPERTY_TYPE_DATA = 0x64,
115 TB_PROPERTY_TYPE_TEXT = 0x74,
116 TB_PROPERTY_TYPE_VALUE = 0x76,
181 TB_LINK_WIDTH_SINGLE = BIT(0),
273 int tb_xdomain_lane_bonding_enable(struct tb_xdomain *xd);
274 void tb_xdomain_lane_bonding_disable(struct tb_xdomain *xd);
275 int tb_xdomain_alloc_in_hopid(struct tb_xdomain *xd, int hopid);
276 void tb_xdomain_release_in_hopid(struct tb_xdomain *xd, in
287 tb_xdomain_disable_all_paths(struct tb_xdomain * xd) tb_xdomain_disable_all_paths() argument
298 struct tb_xdomain *xd; tb_xdomain_find_by_uuid_locked() local
310 struct tb_xdomain *xd; tb_xdomain_find_by_route_locked() local
319 tb_xdomain_get(struct tb_xdomain * xd) tb_xdomain_get() argument
326 tb_xdomain_put(struct tb_xdomain * xd) tb_xdomain_put() argument
[all...]
/linux/drivers/mtd/nand/raw/
H A Dsm_common.c4 * Common routines & support for xD format
21 return 0; in oob_sm_ooblayout_ecc()
28 case 0: in oob_sm_ooblayout_free()
30 oobregion->offset = 0; in oob_sm_ooblayout_free()
47 return 0; in oob_sm_ooblayout_free()
68 oobregion->offset = 0; in oob_sm_small_ooblayout_ecc()
70 return 0; in oob_sm_small_ooblayout_ecc()
77 case 0: in oob_sm_small_ooblayout_free()
91 return 0; in oob_sm_small_ooblayout_free()
107 oob.block_status = 0x0F; in sm_block_markbad()
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_4_2_3_sh_mask.h31 …S_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
32 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
34 …S_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0
35 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL
40 …S_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
41 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
43 …S_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0
44 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL
49 …S_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
50 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
[all …]
H A Ddpcs_3_1_4_sh_mask.h33 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT 0x0
34 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT 0x1
35 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT 0x2
36 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT 0x3
37 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT 0x4
38 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT 0x7
39 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT 0x8
40 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT 0x9
41 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT 0xa
42 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xb
[all …]
H A Ddpcs_4_2_2_sh_mask.h14 …S_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
15 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
17 …S_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0
18 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL
23 …S_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
24 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
26 …S_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0
27 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL
32 …S_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
33 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
[all …]
H A Ddpcs_4_2_0_sh_mask.h27 …S_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
28 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
30 …S_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0
31 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL
36 …S_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
37 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
39 …S_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0
40 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL
45 …S_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
46 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
[all …]
/linux/drivers/thunderbolt/
H A Ddma_test.c19 #define DMA_TEST_DATA_PATTERN 0x0123456789abcdefLL
72 * @xd: XDomain the service belongs to
81 * @link_speed: Expected link speed (Gb/s), %0 to use whatever is negotiated
82 * @link_width: Expected link width (Gb/s), %0 to use whatever is negotiated
94 struct tb_xdomain *xd; member
116 UUID_INIT(0x3188cd10, 0x6523, 0x4a5a,
117 0xa6, 0x82, 0xfd, 0xca, 0x07, 0xa2, 0x48, 0xd8);
125 tb_xdomain_release_in_hopid(dt->xd, dt->rx_hopid); in dma_test_free_rings()
130 tb_xdomain_release_out_hopid(dt->xd, dt->tx_hopid); in dma_test_free_rings()
139 struct tb_xdomain *xd = dt->xd; in dma_test_start_rings() local
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8ulp-pinfunc.h13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0
14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1
15 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0
16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1
17 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0
18 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0
19 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0
20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0
21 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0
22 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0
[all …]
/linux/sound/pci/au88x0/
H A Dau88x0_wt.h12 /* WT channels are grouped in banks. Each bank has 0x20 channels. */
13 /* Bank register address boundary is 0x8000 */
15 #define NR_WT_PB 0x20
18 #define WT_BAR(x) (((x)&0xffe0)<<0x8)
21 #define WT_CTRL(bank) (((((bank)&1)<<0xd) + 0x00)<<2) /* 0x0000 */
22 #define WT_SRAMP(bank) (((((bank)&1)<<0xd) + 0x01)<<2) /* 0x0004 */
23 #define WT_DSREG(bank) (((((bank)&1)<<0xd) + 0x02)<<2) /* 0x0008 */
24 #define WT_MRAMP(bank) (((((bank)&1)<<0xd) + 0x03)<<2) /* 0x000c */
25 #define WT_GMODE(bank) (((((bank)&1)<<0xd) + 0x04)<<2) /* 0x0010 */
26 #define WT_ARAMP(bank) (((((bank)&1)<<0xd) + 0x05)<<2) /* 0x0014 */
[all …]
/linux/drivers/gpio/
H A Dgpio-104-dio-48e.c32 module_param_hw_array(base, uint, ioport, &num_dio48e, 0);
37 module_param_hw_array(irq, uint, irq, &num_irq, 0);
40 #define DIO48E_ENABLE_INTERRUPT 0xB
42 #define DIO48E_ENABLE_COUNTER_TIMER_ADDRESSING 0xD
44 #define DIO48E_CLEAR_INTERRUPT 0xF
49 regmap_reg_range(0x0, 0x9), regmap_reg_range(0xB, 0xB),
50 regmap_reg_range(0xD, 0xD), regmap_reg_range(0xF, 0xF),
53 regmap_reg_range(0x0, 0x2), regmap_reg_range(0x4, 0x6),
54 regmap_reg_range(0xB, 0xB), regmap_reg_range(0xD, 0xD),
55 regmap_reg_range(0xF, 0xF),
[all …]
/linux/drivers/phy/starfive/
H A Dphy-jh7110-dphy-tx.c26 #define STF_DPHY_AON_POWER_READY_N_ACTIVE 0
27 #define STF_DPHY_AON_POWER_READY_N BIT(0)
43 #define STF_DPHY_RG_CDTX_L4N_HSTX_RES GENMASK(4, 0)
45 #define STF_DPHY_RG_CDTX_PLL_FBK_FRA GENMASK(23, 0)
47 #define STF_DPHY_RG_CDTX_PLL_FBK_INT GENMASK(8, 0)
54 #define STF_DPHY_RG_CLANE_HS_CLK_POST_TIME GENMASK(7, 0)
59 #define STF_DPHY_RG_CLANE_HS_ZERO_TIME GENMASK(7, 0)
64 #define STF_DPHY_RG_EXTD_CYCLE_SEL GENMASK(2, 0)
65 #define STF_DPHY_SCFG_C_HS_PRE_ZERO_TIME GENMASK(31, 0)
100 {160000000, 0x6a, 0xaa, 0x3, 0xa, 0x17, 0x11, 0x5, 0x2b, 0xd, 0x7, 0x3d},
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_5_0_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x2
36 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1
[all …]
/linux/drivers/net/phy/mediatek/
H A Dmtk-ge-soc.c14 #define MTK_GPHY_ID_MT7981 0x03a29461
15 #define MTK_GPHY_ID_MT7988 0x03a29481
17 #define MTK_EXT_PAGE_ACCESS 0x1f
18 #define MTK_PHY_PAGE_STANDARD 0x0000
19 #define MTK_PHY_PAGE_EXTENDED_3 0x0003
21 #define MTK_PHY_LPI_REG_14 0x14
22 #define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0)
24 #define MTK_PHY_LPI_REG_1c 0x1c
27 #define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
30 /* ch_addr = 0x0, node_addr = 0x7, data_addr = 0x15 */
[all …]
/linux/drivers/scsi/
H A Dqlogicfas408.h10 again, 0 tends to be slower, but more stable. */
25 #define QL_RESET_AT_START 0
48 /* offset 0xc */
51 #define FASTSCSI 0
54 #define FASTCLK 0 /*(XTALFREQ>25?1:0)*/
69 If this is 0, the bus will only transfer asynchronously */
70 #define SYNCOFFST 0
83 int int_type; /* type of irq, 2 for ISA board, 0 for PCMCIA */
91 #define REG0 ( outb( inb( qbase + 0xd ) & 0x7f , qbase + 0xd ), outb( 4 , qbase + 0xd ))
92 #define REG1 ( outb( inb( qbase + 0xd ) | 0x80 , qbase + 0xd ), outb( 0xb4 | int_type, qbase + 0xd …
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_4_enum.h28 DC_IH_SRC_ID_START = 0x1,
29 DC_IH_SRC_ID_END = 0x1f,
30 VGA_IH_SRC_ID_START = 0x20,
31 VGA_IH_SRC_ID_END = 0x27,
32 CAP_IH_SRC_ID_START = 0x28,
33 CAP_IH_SRC_ID_END = 0x2f,
34 VIP_IH_SRC_ID_START = 0x30,
35 VIP_IH_SRC_ID_END = 0x3f,
36 ROM_IH_SRC_ID_START = 0x40,
37 ROM_IH_SRC_ID_END = 0x5d,
[all …]

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