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/linux/Documentation/devicetree/bindings/usb/
H A Dapple,dwc3.yaml71 reg = <0x82280000 0xcd00>, <0x8228cd00 0x3200>;
74 iommus = <&dwc3_0_dart_0 0>, <&dwc3_0_dart_1 1>;
H A Dqcom,dwc3.yaml159 "^usb@[0-9a-f]+$":
598 reg = <0 0x0a6f8800 0 0x400>;
632 reg = <0 0x0a600000 0 0xcd00>;
634 iommus = <&apps_smmu 0x740 0>;
/linux/drivers/staging/media/meson/vdec/
H A Dhevc_regs.h9 #define HEVC_ASSIST_MMU_MAP_ADDR 0xc024
11 #define HEVC_ASSIST_MBOX1_CLR_REG 0xc1d4
12 #define HEVC_ASSIST_MBOX1_MASK 0xc1d8
14 #define HEVC_ASSIST_SCRATCH_0 0xc300
15 #define HEVC_ASSIST_SCRATCH_1 0xc304
16 #define HEVC_ASSIST_SCRATCH_2 0xc308
17 #define HEVC_ASSIST_SCRATCH_3 0xc30c
18 #define HEVC_ASSIST_SCRATCH_4 0xc310
19 #define HEVC_ASSIST_SCRATCH_5 0xc314
20 #define HEVC_ASSIST_SCRATCH_6 0xc318
[all …]
/linux/arch/arm/boot/dts/socionext/
H A Duniphier-pro4.dtsi18 #size-cells = <0>;
20 cpu@0 {
23 reg = <0>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
65 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
66 <0x506c0000 0x400>;
79 reg = <0x54006000 0x100>;
81 #size-cells = <0>;
84 pinctrl-0 = <&pinctrl_spi0>;
[all …]
H A Duniphier-pro5.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
118 #clock-cells = <0>;
123 #clock-cells = <0>;
138 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
139 <0x506c0000 0x400>;
152 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
153 <0x506c8000 0x400>;
166 reg = <0x54006000 0x100>;
[all …]
H A Duniphier-pxs2.dtsi19 #size-cells = <0>;
21 cpu0: cpu@0 {
24 reg = <0>;
112 #clock-cells = <0>;
117 #clock-cells = <0>;
163 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
164 <0x506c0000 0x400>;
179 reg = <0x54006000 0x100>;
181 #size-cells = <0>;
184 pinctrl-0 = <&pinctrl_spi0>;
[all …]
/linux/sound/soc/codecs/
H A Drt1320-sdw.c31 { 0xc003, 0xe0 },
32 { 0xc01b, 0xfc },
33 { 0xc5c3, 0xf2 },
34 { 0xc5c2, 0x00 },
35 { 0xc5c6, 0x10 },
36 { 0xc5c4, 0x12 },
37 { 0xc5c8, 0x03 },
38 { 0xc5d8, 0x0a },
39 { 0xc5f7, 0x22 },
40 { 0xc5f6, 0x22 },
[all …]
H A Drt1318-sdw.c24 { 0xc001, 0x43 },
25 { 0xc003, 0xa2 },
26 { 0xc004, 0x44 },
27 { 0xc005, 0x44 },
28 { 0xc006, 0x3
[all...]
/linux/drivers/usb/dwc3/
H A Ddwc3-apple.c113 #define APPLE_DWC3_REGS_START 0xcd00
114 #define APPLE_DWC3_REGS_END 0xcdff
116 #define APPLE_DWC3_CIO_LFPS_OFFSET 0xcd38
117 #define APPLE_DWC3_CIO_LFPS_OFFSET_VALUE 0xf800f80
119 #define APPLE_DWC3_CIO_BW_NGT_OFFSET 0xcd3c
120 #define APPLE_DWC3_CIO_BW_NGT_OFFSET_VALUE 0xfc00fc0
122 #define APPLE_DWC3_CIO_LINK_TIMER 0xcd40
124 #define APPLE_DWC3_CIO_PENDING_HP_TIMER_VALUE 0x14
126 #define APPLE_DWC3_CIO_PM_LC_TIMER_VALUE 0xa
127 #define APPLE_DWC3_CIO_PM_ENTRY_TIMER GENMASK(7, 0)
[all …]
H A Ddwc3-qcom-legacy.c28 #define QSCRATCH_HS_PHY_CTRL 0x10
32 #define QSCRATCH_SS_PHY_CTRL 0x30
35 #define QSCRATCH_GENERAL_CFG 0x08
36 #define PIPE_UTMI_CLK_SEL BIT(0)
43 #define SDM845_QSCRATCH_BASE_OFFSET 0xf8800
44 #define SDM845_QSCRATCH_SIZE 0x400
45 #define SDM845_DWC3_CORE_SIZE 0xcd00
52 #define APPS_USB_AVG_BW 0
59 0x58,
60 0x1dc,
[all …]
/linux/include/linux/mfd/
H A Didt8a340_reg.h3 * Based on 5.2.0, Family Programming Guide (Sept 30, 2020)
10 #define PAGE_ADDR_BASE 0x0000
11 #define PAGE_ADDR 0x00fc
13 #define HW_REVISION 0x8180
14 #define REV_ID 0x007a
16 #define HW_DPLL_0 (0x8a00)
17 #define HW_DPLL_1 (0x8b00)
18 #define HW_DPLL_2 (0x8c00)
19 #define HW_DPLL_3 (0x8d00)
20 #define HW_DPLL_4 (0x8e00)
[all …]
/linux/arch/arm/boot/dts/qcom/
H A Dqcom-sdx65.dtsi20 qcom,msm-id = <458 0x10000>, <483 0x10000>, <509 0x10000>;
25 reg = <0 0>;
33 #clock-cells = <0>;
40 #clock-cells = <0>;
46 #clock-cells = <0>;
52 #size-cells = <0>;
54 cpu0: cpu@0 {
57 reg = <0x0>;
115 reg = <0x8fcad000 0x40000>;
120 reg = <0x8fcfd000 0x1000>;
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dagatti.dtsi35 #clock-cells = <0>;
41 #clock-cells = <0>;
47 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0x0 0x0>;
53 clocks = <&cpufreq_hw 0>;
58 qcom,freq-domain = <&cpufreq_hw 0>;
71 reg = <0x0 0x1>;
72 clocks = <&cpufreq_hw 0>;
77 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
/linux/drivers/nvme/host/
H A Dpci.c98 "this size. Use 0 to disable SGLs.");
134 for (i = 0; i < 32; i++) { in nvme_parse_quirk_names()
158 return 0; in nvme_parse_quirk_names()
199 for (i = 0; val[i]; i++) { in quirks_param_set()
210 i = 0; in quirks_param_set()
255 if (ret != 0 || n > blk_mq_num_possible_queues(0)) in io_queue_count_set()
385 #define NVMEQ_ENABLED 0
399 IOD_ABORTED = 1U << 0,
466 memset(dev->dbbuf_dbs, 0, mem_size); in nvme_dbbuf_dma_alloc()
467 memset(dev->dbbuf_eis, 0, mem_size); in nvme_dbbuf_dma_alloc()
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_9_0_offset.h29 // base address: 0x0
30 …BIF_BX0_PCIE_INDEX 0x000c
31 …e regBIF_BX0_PCIE_INDEX_BASE_IDX 0
32 …BIF_BX0_PCIE_DATA 0x000d
33 …e regBIF_BX0_PCIE_DATA_BASE_IDX 0
34 …BIF_BX0_PCIE_INDEX2 0x000e
35 …e regBIF_BX0_PCIE_INDEX2_BASE_IDX 0
36 …BIF_BX0_PCIE_DATA2 0x000f
37 …e regBIF_BX0_PCIE_DATA2_BASE_IDX 0
38 …BIF_BX0_PCIE_INDEX_HI 0x0010
[all …]
/linux/drivers/net/usb/
H A Dr8152.c40 #define PLA_IDR 0xc000
41 #define PLA_RCR 0xc010
42 #define PLA_RCR1 0xc012
43 #define PLA_RMS 0xc016
44 #define PLA_RXFIFO_CTRL0 0xc0a0
45 #define PLA_RXFIFO_FULL 0xc0a2
46 #define PLA_RXFIFO_CTRL1 0xc0a4
47 #define PLA_RX_FIFO_FULL 0xc0a6
48 #define PLA_RXFIFO_CTRL2 0xc0a8
49 #define PLA_RX_FIFO_EMPTY 0xc0aa
[all …]
/linux/fs/nls/
H A Dnls_cp949.c17 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x00-0x07 */
18 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x08-0x0F */
19 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x10-0x17 */
20 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x18-0x1F */
21 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x20-0x27 */
22 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x28-0x2F */
23 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x30-0x37 */
24 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x38-0x3F */
25 0x0000,0xAC02,0xAC03,0xAC05,0xAC06,0xAC0B,0xAC0C,0xAC0D,/* 0x40-0x47 */
26 0xAC0E,0xAC0F,0xAC18,0xAC1E,0xAC1F,0xAC21,0xAC22,0xAC23,/* 0x48-0x4F */
[all …]