28 #define QSCRATCH_HS_PHY_CTRL			0x10
32 #define QSCRATCH_SS_PHY_CTRL			0x30
35 #define QSCRATCH_GENERAL_CFG			0x08
36 #define PIPE_UTMI_CLK_SEL			BIT(0)
43 #define SDM845_QSCRATCH_BASE_OFFSET		0xf8800
44 #define SDM845_QSCRATCH_SIZE			0x400
45 #define SDM845_DWC3_CORE_SIZE			0xcd00
52 #define APPS_USB_AVG_BW 0
59 	0x58,
60 	0x1dc,
61 	0x228,
62 	0x238,
165 		return 0;  in dwc3_qcom_register_extcon()
167 	qcom->edev = extcon_get_edev_by_phandle(dev, 0);  in dwc3_qcom_register_extcon()
180 	if (ret < 0) {  in dwc3_qcom_register_extcon()
193 	if (ret < 0) {  in dwc3_qcom_register_extcon()
205 	return 0;  in dwc3_qcom_register_extcon()
282 	return 0;  in dwc3_qcom_interconnect_init()
382 	dwc3_qcom_enable_wakeup_irq(port->qusb2_phy_irq, 0);  in dwc3_qcom_enable_port_interrupts()
407 	dwc3_qcom_enable_wakeup_irq(port->ss_phy_irq, 0);  in dwc3_qcom_enable_port_interrupts()
414 	for (i = 0; i < qcom->num_ports; i++)  in dwc3_qcom_disable_interrupts()
422 	for (i = 0; i < qcom->num_ports; i++)  in dwc3_qcom_enable_interrupts()
432 		return 0;  in dwc3_qcom_suspend()
434 	for (i = 0; i < qcom->num_ports; i++) {  in dwc3_qcom_suspend()
440 	for (i = qcom->num_clocks - 1; i >= 0; i--)  in dwc3_qcom_suspend()
452 		for (i = 0; i < qcom->num_ports; i++)  in dwc3_qcom_suspend()
459 	return 0;  in dwc3_qcom_suspend()
468 		return 0;  in dwc3_qcom_resume()
473 	for (i = 0; i < qcom->num_clocks; i++) {  in dwc3_qcom_resume()
475 		if (ret < 0) {  in dwc3_qcom_resume()
476 			while (--i >= 0)  in dwc3_qcom_resume()
487 	for (i = 0; i < qcom->num_ports; i++) {  in dwc3_qcom_resume()
495 	return 0;  in dwc3_qcom_resume()
565 	if (irq > 0) {  in dwc3_qcom_setup_port_irq()
580 	if (irq > 0) {  in dwc3_qcom_setup_port_irq()
595 	if (irq > 0) {  in dwc3_qcom_setup_port_irq()
603 		return 0;  in dwc3_qcom_setup_port_irq()
606 	if (irq > 0) {  in dwc3_qcom_setup_port_irq()
613 	return 0;  in dwc3_qcom_setup_port_irq()
623 	if (irq <= 0)  in dwc3_qcom_find_num_ports()
630 		if (irq <= 0)  in dwc3_qcom_find_num_ports()
647 	for (i = 0; i < qcom->num_ports; i++) {  in dwc3_qcom_setup_irq()
653 	return 0;  in dwc3_qcom_setup_irq()
663 		return 0;  in dwc3_qcom_clk_init()
665 	if (count < 0)  in dwc3_qcom_clk_init()
675 	for (i = 0; i < qcom->num_clocks; i++) {  in dwc3_qcom_clk_init()
681 			while (--i >= 0)  in dwc3_qcom_clk_init()
687 		if (ret < 0) {  in dwc3_qcom_clk_init()
688 			while (--i >= 0) {  in dwc3_qcom_clk_init()
700 	return 0;  in dwc3_qcom_clk_init()
775 	qcom->qscratch_base = devm_platform_ioremap_resource(pdev, 0);  in dwc3_qcom_probe()
826 	return 0;  in dwc3_qcom_probe()
834 	for (i = qcom->num_clocks - 1; i >= 0; i--) {  in dwc3_qcom_probe()
853 	for (i = qcom->num_clocks - 1; i >= 0; i--) {  in dwc3_qcom_remove()
857 	qcom->num_clocks = 0;  in dwc3_qcom_remove()
878 	return 0;  in dwc3_qcom_pm_suspend()
893 	return 0;  in dwc3_qcom_pm_resume()