/freebsd/sys/contrib/device-tree/src/arm/intel/ixp/ |
H A D | intel-ixp43x.dtsi | 13 /* Uses at least up to 0x230 */ 14 reg = <0xc4000000 0x1000>;
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H A D | intel-ixp42x.dtsi | 12 reg = <0xc4000000 0x30>; 29 reg = <0xc800b000 0x1000>;
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H A D | intel-ixp45x-ixp46x.dtsi | 14 /* Uses at least up to 0x124 */ 15 reg = <0xc4000000 0x1000>; 20 reg = <0x70002100 4>; 33 reg = <0xc800b000 0x1000>; 40 reg = <0xc8011000 0x18>; 48 reg = <0xc800d000 0x1000>; 52 queue-rx = <&qmgr 0>; 53 queue-txready = <&qmgr 0>; 59 reg = <0xc800e000 0x1000>; 63 queue-rx = <&qmgr 0>; [all …]
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/freebsd/sys/contrib/device-tree/Bindings/ata/ |
H A D | intel,ixp4xx-compact-flash.yaml | 48 reg = <0xc4000000 0x1000>; 52 ranges = <0 0x0 0x50000000 0x01000000>, <1 0x0 0x51000000 0x01000000>; 53 dma-ranges = <0 0x0 0x50000000 0x01000000>, <1 0x0 0x51000000 0x01000000>; 54 ide@1,0 { 56 reg = <1 0x00000000 0x1000>, <1 0x00040000 0x1000>;
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/freebsd/sys/contrib/device-tree/src/riscv/microchip/ |
H A D | mpfs-sev-kit.dts | 35 reg = <0x0 0x80000000 0x0 0x2000000>; 40 reg = <0x0 0xc4000000 0x0 0x4000000>; 45 reg = <0x [all...] |
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ |
H A D | intel,ixp4xx-expansion-bus-controller.yaml | 19 pattern: '^bus@[0-9a-f]+$' 55 "^.*@[0-7],[0-9a-f]+$": 78 reg = <0xc4000000 0x28>; 82 ranges = <0 0x0 0x50000000 0x01000000>, 83 <1 0x0 0x51000000 0x01000000>; 84 dma-ranges = <0 0x0 0x50000000 0x01000000>, 85 <1 0x0 0x51000000 0x01000000>; 86 flash@0,0 { 89 reg = <0 0x00000000 0x1000000>; 91 intel,ixp4xx-eb-cycle-type = <0>; [all …]
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/freebsd/sys/contrib/device-tree/Bindings/infiniband/ |
H A D | hisilicon-hns-roce.txt | 25 - hns-roce-comp-0 ~ hns-roce-comp-31: 32 complete event irq 31 reg = <0x0 0xc4000000 0x0 0x100000>; 74 interrupt-names = "hns-roce-comp-0",
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/freebsd/sys/contrib/device-tree/src/arm/nspire/ |
H A D | nspire.dtsi | 13 #size-cells = <0>; 15 cpu@0 { 18 reg = <0>; 22 bootrom: bootrom@0 { 23 reg = <0x00000000 0x80000>; 28 reg = <0xa4000000 0x20000>; /* 128k */ 31 ranges = <0 0xa4000000 0x20000>; 33 sram@0 { 34 reg = <0x0 0x20000>; 39 #clock-cells = <0>; [all …]
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/freebsd/sys/contrib/device-tree/Bindings/bus/ |
H A D | intel,ixp4xx-expansion-bus-controller.yaml | 19 pattern: '^bus@[0-9a-f]+$' 55 "^.*@[0-7],[0-9a-f]+$": 88 chip select. 0 = Intel cycles, 1 = Motorola cycles, 2 = HPI cycles. 90 enum: [0, 1, 2] 95 enum: [0, 1] 100 enum: [0, 1] 105 enum: [0, 1] 110 enum: [0, 1] 115 enum: [0, 1] 121 enum: [0, 1] [all …]
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/freebsd/sys/contrib/openzfs/module/icp/asm-x86_64/aes/ |
H A D | aestab2.h | 49 0x00000001, 0x00000002, 0x00000004, 0x00000008, 50 0x00000010, 0x00000020, 0x00000040, 0x00000080, 51 0x0000001b, 0x00000036 57 0x00000063, 0x0000007c, 0x00000077, 0x0000007b, 58 0x000000f2, 0x0000006b, 0x0000006f, 0x000000c5, 59 0x00000030, 0x00000001, 0x00000067, 0x0000002b, 60 0x000000fe, 0x000000d7, 0x000000ab, 0x00000076, 61 0x000000ca, 0x00000082, 0x000000c9, 0x0000007d, 62 0x000000fa, 0x00000059, 0x00000047, 0x000000f0, 63 0x000000ad, 0x000000d4, 0x000000a2, 0x000000af, [all …]
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/freebsd/sys/powerpc/powerpc/ |
H A D | db_disasm.c | 17 Op_A = 0x00000001, 18 Op_B = 0x00000002, 19 Op_BI = 0x00000004, 20 Op_BO = 0x00000008, 22 Op_CRM = 0x00000010, 23 Op_D = 0x00000020, 24 Op_ST = 0x00000020, /* Op_S for store-operations, same as D */ 25 Op_S = 0x00000040, /* S-field is swapped with A-field */ 27 Op_dA = 0x00000080, 28 Op_LK = 0x00000100, [all …]
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/freebsd/sys/contrib/device-tree/src/arm64/hisilicon/ |
H A D | hip07.dtsi | 23 #size-cells = <0>; 270 reg = <0x10000>; 273 numa-node-id = <0>; 279 reg = <0x10001>; 282 numa-node-id = <0>; 288 reg = <0x10002>; 291 numa-node-id = <0>; 297 reg = <0x10003>; 300 numa-node-id = <0>; 306 reg = <0x10100>; [all …]
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/freebsd/tools/test/iconv/ref/ |
H A D | UTF-32BE-rev | 1 0x00 = 0x00000000 2 0x01 = 0x01000000 3 0x02 = 0x02000000 4 0x03 = 0x03000000 5 0x04 = 0x04000000 6 0x05 = 0x05000000 7 0x06 = 0x06000000 8 0x07 = 0x07000000 9 0x08 = 0x08000000 10 0x09 = 0x09000000 [all …]
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/freebsd/sys/dev/qlnx/qlnxe/ |
H A D | ecore_init_values.h | 35 0x00030003, 0xffff0000, /* if phase != 'engine', skip 3 ops (no DMAE) */ 36 0x00020002, 0x00020000, /* if mode != '!asic', skip 2 ops */ 37 0x0280c201, 0x00000000, /* write 0x0 to address 0x50184 */ 38 0x02810201, 0x00000000, /* write 0x0 to address 0x50204 */ 40 0x00110003, 0xffff0000, /* if phase != 'engine', skip 17 ops (no DMAE) */ 41 0x00030002, 0x00020000, /* if mode != '!asic', skip 3 ops */ 42 0x0048c201, 0x00000000, /* write 0x0 to address 0x9184 */ 43 0x0048d201, 0x00000000, /* write 0x0 to address 0x91a4 */ 44 0x004ba601, 0x00000001, /* write 0x1 to address 0x974c */ 45 0x00020002, 0x00be0000, /* if mode != '(!asic)&bb', skip 2 ops */ [all …]
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