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/freebsd/bin/pax/tests/
H A Dlegacy_test.pl9 my $n = 0;
49 my $n = 0;
52 ok($? == 0, "Wrote 'ustar.ok' containing files with lengths @l");
59 ok($? == 0, "Restored 'ustar.ok' containing files with lengths @l");
62 ok($? == 0, "Restored files are identical");
76 $paths[-1] = "$work94/${x95}xc100"; # 100 char filename
83 $paths[-1] = "$work94/${x95}xc100/x"; # 100 char component
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dpq3-dma-1.dtsi2 * PQ3 DMA device tree stub [ controller @ offset 0xc300 ]
39 reg = <0xc300 0x4>;
40 ranges = <0x0 0xc100 0x200>;
42 dma-channel@0 {
44 reg = <0x0 0x80>;
45 cell-index = <0>;
46 interrupts = <76 2 0 0>;
50 reg = <0x80 0x80>;
52 interrupts = <77 2 0 0>;
56 reg = <0x100 0x80>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am65-iot2050-common-pg1.dtsi59 dmas = <&main_udmap 0xc100>, /* egress slice 0 */
60 <&main_udmap 0xc101>, /* egress slice 0 */
61 <&main_udmap 0xc102>, /* egress slice 0 */
62 <&main_udmap 0xc103>, /* egress slice 0 */
63 <&main_udmap 0xc104>, /* egress slice 1 */
64 <&main_udmap 0xc105>, /* egress slice 1 */
65 <&main_udmap 0xc106>, /* egress slice 1 */
66 <&main_udmap 0xc107>, /* egress slice 1 */
67 <&main_udmap 0x4100>, /* ingress slice 0 */
68 <&main_udmap 0x4101>, /* ingress slice 1 */
[all …]
H A Dk3-am654-idk.dtso17 ethernet3 = "/icssg0-eth/ethernet-ports/port@0";
19 ethernet5 = "/icssg1-eth/ethernet-ports/port@0";
27 pinctrl-0 = <&icssg0_rgmii_pins_default>;
49 interrupts = <24 0 2>, <25 1 3>;
52 dmas = <&main_udmap 0xc100>, /* egress slice 0 */
53 <&main_udmap 0xc101>, /* egress slice 0 */
54 <&main_udmap 0xc102>, /* egress slice 0 */
55 <&main_udmap 0xc103>, /* egress slice 0 */
56 <&main_udmap 0xc104>, /* egress slice 1 */
57 <&main_udmap 0xc105>, /* egress slice 1 */
[all …]
H A Dk3-am642-phyboard-electra-rdk.dts45 pinctrl-0 = <&can_tc1_pins_default>;
46 #phy-cells = <0>;
54 pinctrl-0 = <&can_tc2_pins_default>;
55 #phy-cells = <0>;
64 pinctrl-0 = <&icssg0_rgmii1_pins_default>, <&icssg0_rgmii2_pins_default>;
67 interrupts = <24 0 2>, <25 1 3>;
78 dmas = <&main_pktdma 0xc100 15>, /* egress slice 0 */
79 <&main_pktdma 0xc101 15>, /* egress slice 0 */
80 <&main_pktdma 0xc102 15>, /* egress slice 0 */
81 <&main_pktdma 0xc103 15>, /* egress slice 0 */
[all …]
H A Dk3-am65-iot2050-common.dtsi45 reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */
46 alignment = <0x1000>;
52 reg = <0 0xa0000000 0 0x100000>;
58 reg = <0 0xa0100000 0 0xf00000>;
64 reg = <0 0xa1000000 0 0x100000>;
70 reg = <0 0xa1100000 0 0xf00000>;
75 reg = <0x00 0xa2000000 0x00 0x00200000>;
76 alignment = <0x1000>;
82 reg = <0x00 0xa2200000 0x00 0x1000>;
90 pinctrl-0 = <&leds_pins_default>;
[all …]
/freebsd/sys/dev/usb/controller/dwc3/
H A Ddwc3.h32 #define DWC3_IP_ID 0x5533
33 #define DWC3_1_IP_ID 0x3331
34 #define DWC3_2_IP_ID 0x3332
36 #define DWC3_VERSION_MASK 0xFFFF0000
37 #define DWC3_REVISION_MASK 0xFFFF
41 #define DWC3_GSBUSCFG0 0xc100
42 #define DWC3_GSBUSCFG1 0xc104
43 #define DWC3_GTXTHRCFG 0xc108
44 #define DWC3_GRXTHRCFG 0xc10C
47 #define DWC3_GCTL 0xc110
[all …]
/freebsd/sys/contrib/device-tree/Bindings/interconnect/
H A Dqcom,sdm660.yaml90 reg = <0x01008000 0x78000>;
96 reg = <0x01704000 0xc100>;
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsdm632-motorola-ocean.dts18 qcom,msm-id = <349 0>;
19 qcom,board-id = <0x141 0xc100>;
20 qcom,pmic-id = <0x10016 0x25 0x00 0x00>;
34 reg = <0 0x90001000 0 (720 * 1520 * 3)>;
57 pinctrl-0 = <&gpio_key_default>;
68 reg = <0x0 0x84300000 0x0 0x2000000>;
73 reg = <0x0 0x90001000 0x0 (720 * 1520 * 3)>;
78 reg = <0x00 0xeefa1800 0x00 0x5e800>;
84 reg = <0x0 0xef000000 0x0 0xbf800>;
85 console-size = <0x40000>;
[all …]
H A Dsdm630.dtsi35 #clock-cells = <0>;
42 #clock-cells = <0>;
50 #size-cells = <0>;
55 reg = <0x0 0x100>;
75 reg = <0x0 0x101>;
90 reg = <0x0 0x102>;
105 reg = <0x0 0x103>;
117 CPU4: cpu@0 {
120 reg = <0x0 0x0>;
140 reg = <0x0 0x1>;
[all …]
/freebsd/sys/contrib/dev/rtw89/
H A Drtw8852c_rfk_table.c8 RTW89_DECL_RFK_WM(0xc004, BIT(17), 0x1),
9 RTW89_DECL_RFK_WM(0xc024, BIT(17), 0x1),
10 RTW89_DECL_RFK_WM(0xc104, BIT(17), 0x1),
11 RTW89_DECL_RFK_WM(0xc124, BIT(17), 0x1),
17 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x
[all...]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dmpc8610_hpcd.dts26 #size-cells = <0>;
28 PowerPC,8610@0 {
30 reg = <0>;
35 sleep = <&pmc 0x00008000 0 // core
36 &pmc 0x00004000 0>; // timebase
37 timebase-frequency = <0>; // From uboot
38 bus-frequency = <0>; // From uboot
39 clock-frequency = <0>; // From uboot
45 reg = <0x00000000 0x20000000>; // 512M at 0x0
52 reg = <0xe0005000 0x1000>;
[all …]
H A Dxpedite5301.dts16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
29 #size-cells = <0>;
31 PowerPC,8572@0 {
33 reg = <0x0>;
36 d-cache-size = <0x8000>; // L1, 32K
37 i-cache-size = <0x8000>; // L1, 32K
38 timebase-frequency = <0>;
39 bus-frequency = <0>;
40 clock-frequency = <0>;
46 reg = <0x1>;
[all …]
H A Dxpedite5370.dts27 #size-cells = <0>;
29 PowerPC,8572@0 {
31 reg = <0x0>;
34 d-cache-size = <0x8000>; // L1, 32K
35 i-cache-size = <0x8000>; // L1, 32K
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
44 reg = <0x1>;
47 d-cache-size = <0x8000>; // L1, 32K
[all …]
H A Dxcalibur1501.dts28 #size-cells = <0>;
30 PowerPC,8572@0 {
32 reg = <0x0>;
35 d-cache-size = <0x8000>; // L1, 32K
36 i-cache-size = <0x8000>; // L1, 32K
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
45 reg = <0x1>;
48 d-cache-size = <0x8000>; // L1, 32K
[all …]
H A Dxpedite5330.dts16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
30 #size-cells = <0>;
32 pmcslot@0 {
33 cell-index = <0>;
44 #size-cells = <0>;
46 xmcslot@0 {
47 cell-index = <0>;
65 #size-cells = <0>;
67 PowerPC,8572@0 {
69 reg = <0x0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Darmada-39x.dtsi32 #size-cells = <0>;
35 cpu@0 {
38 reg = <0>;
59 pcie-mem-aperture = <0xe0000000 0x8000000>;
60 pcie-io-aperture = <0xe8000000 0x100000>;
64 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
71 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
75 reg = <0x8000 0x1000>;
78 arm,double-linefill-incr = <0>;
79 arm,double-linefill-wrap = <0>;
[all …]
H A Darmada-375.dtsi36 #clock-cells = <0>;
42 #clock-cells = <0>;
49 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0>;
75 pcie-mem-aperture = <0xe0000000 0x8000000>;
76 pcie-io-aperture = <0xe8000000 0x100000>;
80 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
85 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
86 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
[all …]
H A Darmada-38x.dtsi42 pcie-mem-aperture = <0xe0000000 0x8000000>;
43 pcie-io-aperture = <0xe8000000 0x100000>;
47 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
52 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
53 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
56 clocks = <&coreclk 0>;
62 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
63 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
66 clocks = <&coreclk 0>;
72 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
[all …]
/freebsd/sys/dts/powerpc/
H A Dp2020ds.dts81 #size-cells = <0>;
83 PowerPC,P2020@0 {
85 reg = <0x0>;
91 reg = <0x1>;
104 reg = <0 0xffe05000 0 0x1000>;
108 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
109 0x1 0x0 0x0 0xe0000000 0x08000000
110 0x2 0x0 0x0 0xffa00000 0x00040000
111 0x3 0x0 0x0 0xffdf0000 0x00008000
112 0x4 0x0 0x0 0xffa40000 0x00040000
[all …]
H A Dmpc8572ds.dts82 #size-cells = <0>;
84 PowerPC,8572@0 {
86 reg = <0x0>;
89 d-cache-size = <0x8000>; // L1, 32K
90 i-cache-size = <0x8000>; // L1, 32K
91 timebase-frequency = <0>;
92 bus-frequency = <0>;
93 clock-frequency = <0>;
99 reg = <0x1>;
102 d-cache-size = <0x8000>; // L1, 32K
[all …]
/freebsd/sys/arm64/freescale/imx/
H A Dimx8mp_ccm.c350 FIXED(IMX8MP_CLK_DUMMY, "dummy", 0),
359 MUX(IMX8MP_AUDIO_PLL1_REF_SEL, "audio_pll1_ref_sel", pll_ref_p, 0, 0x00, 0, 2),
360 MUX(IMX8MP_AUDIO_PLL2_REF_SEL, "audio_pll2_ref_sel", pll_ref_p, 0, 0x14, 0, 2),
361 MUX(IMX8MP_VIDEO_PLL1_REF_SEL, "video_pll1_ref_sel", pll_ref_p, 0, 0x28, 0, 2),
362 MUX(IMX8MP_DRAM_PLL_REF_SEL, "dram_pll_ref_sel", pll_ref_p, 0, 0x50, 0, 2),
363 MUX(IMX8MP_GPU_PLL_REF_SEL, "gpu_pll_ref_sel", pll_ref_p, 0, 0x64, 0, 2),
364 MUX(IMX8MP_VPU_PLL_REF_SEL, "vpu_pll_ref_sel", pll_ref_p, 0, 0x74, 0, 2),
365 MUX(IMX8MP_ARM_PLL_REF_SEL, "arm_pll_ref_sel", pll_ref_p, 0, 0x84, 0, 2),
366 MUX(IMX8MP_SYS_PLL1_REF_SEL, "sys_pll1_ref_sel", pll_ref_p, 0, 0x94, 0, 2),
367 MUX(IMX8MP_SYS_PLL2_REF_SEL, "sys_pll2_ref_sel", pll_ref_p, 0, 0x104, 0, 2),
[all …]
/freebsd/crypto/openssl/ssl/
H A Dt1_trce.c36 for (i = 0; i < ntbl; i++, tbl++) { in do_ssl_trace_str()
50 return 0; in do_ssl_trace_list()
52 val = msg[0]; in do_ssl_trace_list()
112 {0x0000, "TLS_NULL_WITH_NULL_NULL"},
113 {0x0001, "TLS_RSA_WITH_NULL_MD5"},
114 {0x0002, "TLS_RSA_WITH_NULL_SHA"},
115 {0x0003, "TLS_RSA_EXPORT_WITH_RC4_40_MD5"},
116 {0x0004, "TLS_RSA_WITH_RC4_128_MD5"},
117 {0x0005, "TLS_RSA_WITH_RC4_128_SHA"},
118 {0x0006, "TLS_RSA_EXPORT_WITH_RC2_CBC_40_MD5"},
[all …]
/freebsd/share/i18n/csmapper/KS/
H A DKSC5601HANGUL%UCS.src5 SRC_ZONE 0x24-0x48 / 0x21-0x7E / 8
7 DST_INVALID 0xFFFE
50 # egrep '^0x' < KSC5601.TXT | \
51 # egrep -v '^0x([8-9]...|A0..|..[4-9].|..A0)' | perl tab.pl
55 # $n=0;
60 # printf ("0x%04X 0x%04X %s\n",$k-0x8080, $u,join(' ',@rest));
65 # in hex as 0xXXXX
66 # Column #2 : the Unicode (in hex as 0xXXXX)
74 # To get EUC Korean(EUC-KR) code points, add 0x8080.
76 # first subtract 0x2020. Then
[all …]
H A DUCS%KSC5601HANGUL.src5 SRC_ZONE 0x3131 - 0xD79D
7 DST_INVALID 0xFFFF
50 # egrep '^0x' < KSC5601.TXT | \
51 # egrep -v '^0x([8-9]...|A0..|..[4-9].|..A0)' | perl tab.pl
55 # $n=0;
60 # printf ("0x%04X 0x%04X %s\n",$k-0x8080, $u,join(' ',@rest));
65 # in hex as 0xXXXX
66 # Column #2 : the Unicode (in hex as 0xXXXX)
74 # To get EUC Korean(EUC-KR) code points, add 0x8080.
76 # first subtract 0x2020. Then
[all …]

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