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12

/freebsd/sys/powerpc/mpc85xx/
H A Dmpc85xx.h42 #define OCP85XX_CCSRBAR (CCSRBAR_VA + 0x0)
43 #define OCP85XX_BPTR (CCSRBAR_VA + 0x20)
45 #define OCP85XX_BSTRH (CCSRBAR_VA + 0x20)
46 #define OCP85XX_BSTRL (CCSRBAR_VA + 0x24)
47 #define OCP85XX_BSTAR (CCSRBAR_VA + 0x28)
49 #define OCP85XX_COREDISR (CCSRBAR_VA + 0xE0094)
50 #define OCP85XX_BRR (CCSRBAR_VA + 0xE00E4)
55 #define CCSR_CTBENR (CCSRBAR_VA + 0xE2084)
56 #define CCSR_CTBCKSELR (CCSRBAR_VA + 0xE208C)
57 #define CCSR_CTBCHLTCR (CCSRBAR_VA + 0xE2094)
[all …]
/freebsd/sys/arm/include/
H A Dcpuinfo.h33 #define CPU_IMPLEMENTER_ARM 0x41
34 #define CPU_IMPLEMENTER_QCOM 0x51
35 #define CPU_IMPLEMENTER_MRVL 0x56
38 #define CPU_ARCH_ARM1176 0xB76
39 #define CPU_ARCH_CORTEX_A5 0xC05
40 #define CPU_ARCH_CORTEX_A7 0xC07
41 #define CPU_ARCH_CORTEX_A8 0xC08
42 #define CPU_ARCH_CORTEX_A9 0xC09
43 #define CPU_ARCH_CORTEX_A12 0xC0D
44 #define CPU_ARCH_CORTEX_A15 0xC0F
[all …]
/freebsd/sys/dev/qat/include/
H A Dadf_dev_err.h10 #define ADF_ERRSOU0 (0x3A000 + 0x00)
11 #define ADF_ERRSOU1 (0x3A000 + 0x04)
12 #define ADF_ERRSOU2 (0x3A000 + 0x08)
13 #define ADF_ERRSOU3 (0x3A000 + 0x0C)
14 #define ADF_ERRSOU4 (0x3A000 + 0xD0)
15 #define ADF_ERRSOU5 (0x3A000 + 0xD8)
16 #define ADF_ERRMSK0 (0x3A000 + 0x10)
17 #define ADF_ERRMSK1 (0x3A000 + 0x14)
18 #define ADF_ERRMSK2 (0x3A000 + 0x18)
19 #define ADF_ERRMSK3 (0x3A000 + 0x1C)
[all …]
/freebsd/sys/contrib/dev/rtw88/
H A Drtw8822b.h13 u8 res4[4]; /* 0xd0 */
15 u8 res5[0x1e];
17 u8 serial[0x0b]; /* 0xf5 */
18 u8 vid; /* 0x100 */
22 u8 mac_addr[ETH_ALEN]; /* 0x107 */
24 u8 vendor_name[0x07];
26 u8 device_name[0x14];
27 u8 res11[0xcf];
28 u8 package_type; /* 0x1f
[all...]
H A Drtw8821c.h13 u8 res4[4]; /* 0xd0 */
15 u8 res5[0x1e];
17 u8 serial[0x0b]; /* 0xf5 */
18 u8 vid; /* 0x100 */
22 u8 mac_addr[ETH_ALEN]; /* 0x107 */
24 u8 vendor_name[0x07];
26 u8 device_name[0x14];
27 u8 res11[0xcf];
28 u8 package_type; /* 0x1f
[all...]
H A Drtw8723x.c19 [DESC_RATE1M] = { .addr = 0xe08, .mask = 0x0000ff00 },
20 [DESC_RATE2M] = { .addr = 0x86c, .mask = 0x0000ff00 },
21 [DESC_RATE5_5M] = { .addr = 0x86c, .mask = 0x00ff0000 },
22 [DESC_RATE11M] = { .addr = 0x86c, .mask = 0xff000000 },
23 [DESC_RATE6M] = { .addr = 0xe00, .mask = 0x000000ff },
24 [DESC_RATE9M] = { .addr = 0xe00, .mask = 0x0000ff00 },
25 [DESC_RATE12M] = { .addr = 0xe00, .mask = 0x00ff0000 },
26 [DESC_RATE18M] = { .addr = 0xe00, .mask = 0xff000000 },
27 [DESC_RATE24M] = { .addr = 0xe04, .mask = 0x000000ff },
28 [DESC_RATE36M] = { .addr = 0xe04, .mask = 0x0000ff00 },
[all …]
H A Drtw8723d_table.c10 0x020, 0x00000013,
11 0x02F, 0x00000010,
12 0x077, 0x00000007,
13 0x421, 0x0000000F,
14 0x428, 0x0000000A,
15 0x429, 0x00000010,
16 0x430, 0x00000000,
17 0x431, 0x00000000,
18 0x432, 0x00000000,
19 0x433, 0x00000001,
[all …]
H A Drtw8821c_table.c10 0x010, 0x00000043,
11 0x025, 0x0000001D,
12 0x026, 0x000000CE,
13 0x04F, 0x00000001,
14 0x029, 0x000000F
[all...]
/freebsd/sys/dev/rtwn/rtl8192c/usb/
H A Dr92cu_priv.h29 { 0x420, 0x80 }, { 0x423, 0x00 }, { 0x430, 0x00 }, { 0x431, 0x00 },
30 { 0x432, 0x00 }, { 0x433, 0x01 }, { 0x434, 0x04 }, { 0x435, 0x05 },
31 { 0x436, 0x06 }, { 0x437, 0x07 }, { 0x438, 0x00 }, { 0x439, 0x00 },
32 { 0x43a, 0x00 }, { 0x43b, 0x01 }, { 0x43c, 0x04 }, { 0x43d, 0x05 },
33 { 0x43e, 0x06 }, { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 },
34 { 0x442, 0x00 }, { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f },
35 { 0x447, 0x00 }, { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 },
36 { 0x45b, 0xb9 }, { 0x460, 0x66 }, { 0x461, 0x66 }, { 0x462, 0x08 },
37 { 0x463, 0x03 }, { 0x4c8, 0xff }, { 0x4c9, 0x08 }, { 0x4cc, 0xff },
38 { 0x4cd, 0xff }, { 0x4ce, 0x01 }, { 0x500, 0x26 }, { 0x501, 0xa2 },
[all …]
/freebsd/sys/dev/bhnd/cores/pcie2/
H A Dbhnd_pcie2_reg.h31 #define BHND_PCIE2_DMA64_TRANSLATION 0x8000000000000000 /**< PCIe-Gen2 DMA64 address translation */
32 #define BHND_PCIE2_DMA64_MASK 0xc000000000000000 /**< PCIe-Gen2 DMA64 translation mask */
38 #define BHND_PCIE2_CLK_CONTROL 0x000
40 #define BHND_PCIE2_RC_PM_CONTROL 0x004
41 #define BHND_PCIE2_RC_PM_STATUS 0x008
42 #define BHND_PCIE2_EP_PM_CONTROL 0x00C
43 #define BHND_PCIE2_EP_PM_STATUS 0x010
44 #define BHND_PCIE2_EP_LTR_CONTROL 0x014
45 #define BHND_PCIE2_EP_LTR_STATUS 0x018
46 #define BHND_PCIE2_EP_OBFF_STATUS 0x01C
[all …]
/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dqcom,sdm670-camss.yaml107 port@0:
205 reg = <0 0x0acb3000 0 0x1000>,
206 <0 0x0acba000 0 0x1000>,
207 <0 0x0acc8000 0 0x1000>,
208 <0 0x0ac65000 0 0x1000>,
209 <0 0x0ac66000 0 0x1000>,
210 <0 0x0ac67000 0 0x1000>,
211 <0 0x0acaf000 0 0x4000>,
212 <0 0x0acb6000 0 0x4000>,
213 <0 0x0acc4000 0 0x4000>;
[all …]
/freebsd/sys/dev/rtwn/rtl8192c/pci/
H A Dr92ce_priv.h31 { 0x420, 0x80 }, { 0x423, 0x00 }, { 0x430, 0x00 }, { 0x431, 0x00 },
32 { 0x432, 0x00 }, { 0x433, 0x01 }, { 0x434, 0x04 }, { 0x435, 0x05 },
33 { 0x436, 0x06 }, { 0x437, 0x07 }, { 0x438, 0x00 }, { 0x439, 0x00 },
34 { 0x43a, 0x00 }, { 0x43b, 0x01 }, { 0x43c, 0x04 }, { 0x43d, 0x05 },
35 { 0x43e, 0x06 }, { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 },
36 { 0x442, 0x00 }, { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f },
37 { 0x447, 0x00 }, { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 },
38 { 0x45b, 0xb9 }, { 0x460, 0x88 }, { 0x461, 0x88 }, { 0x462, 0x06 },
39 { 0x463, 0x03 }, { 0x4c8, 0x04 }, { 0x4c9, 0x08 }, { 0x4cc, 0x02 },
40 { 0x4cd, 0x28 }, { 0x4ce, 0x01 }, { 0x500, 0x26 }, { 0x501, 0xa2 },
[all …]
/freebsd/sys/dev/qcom_ess_edma/
H A Dqcom_ess_edma_reg.h63 #define EDMA_REG_MAS_CTRL 0x0
64 #define EDMA_REG_TIMEOUT_CTRL 0x004
65 #define EDMA_REG_DBG0 0x008
66 #define EDMA_REG_DBG1 0x00C
67 #define EDMA_REG_SW_CTRL0 0x100
68 #define EDMA_REG_SW_CTRL1 0x104
71 #define EDMA_REG_RX_ISR 0x200
72 #define EDMA_REG_TX_ISR 0x208
73 #define EDMA_REG_MISC_ISR 0x210
74 #define EDMA_REG_WOL_ISR 0x218
[all …]
/freebsd/sys/dev/rtwn/rtl8188e/
H A Dr88e_priv.h39 { 0x026, 0x41 }, { 0x027, 0x35 }, { 0x040, 0x00 }, { 0x428, 0x0a },
40 { 0x429, 0x10 }, { 0x430, 0x00 }, { 0x431, 0x01 }, { 0x432, 0x02 },
41 { 0x433, 0x04 }, { 0x434, 0x05 }, { 0x435, 0x06 }, { 0x436, 0x07 },
42 { 0x437, 0x08 }, { 0x438, 0x00 }, { 0x439, 0x00 }, { 0x43a, 0x01 },
43 { 0x43b, 0x02 }, { 0x43c, 0x04 }, { 0x43d, 0x05 }, { 0x43e, 0x06 },
44 { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 }, { 0x442, 0x00 },
45 { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f }, { 0x447, 0x00 },
46 { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 }, { 0x45b, 0xb9 },
47 { 0x460, 0x66 }, { 0x461, 0x66 }, { 0x480, 0x08 }, { 0x4c8, 0xff },
48 { 0x4c9, 0x08 }, { 0x4cc, 0xff }, { 0x4cd, 0xff }, { 0x4ce, 0x01 },
[all …]
/freebsd/sys/dev/rtwn/rtl8192e/
H A Dr92e_priv.h34 { 0x011, 0xeb }, { 0x012, 0x07 }, { 0x014, 0x75 }, { 0x303, 0xa7 },
35 { 0x428, 0x0a }, { 0x429, 0x10 }, { 0x430, 0x00 }, { 0x431, 0x00 },
36 { 0x432, 0x00 }, { 0x433, 0x01 }, { 0x434, 0x04 }, { 0x435, 0x05 },
37 { 0x436, 0x07 }, { 0x437, 0x08 }, { 0x43c, 0x04 }, { 0x43d, 0x05 },
38 { 0x43e, 0x07 }, { 0x43f, 0x08 }, { 0x440, 0x5d }, { 0x441, 0x01 },
39 { 0x442, 0x00 }, { 0x444, 0x10 }, { 0x445, 0x00 }, { 0x446, 0x00 },
40 { 0x447, 0x00 }, { 0x448, 0x00 }, { 0x449, 0xf0 }, { 0x44a, 0x0f },
41 { 0x44b, 0x3e }, { 0x44c, 0x10 }, { 0x44d, 0x00 }, { 0x44e, 0x00 },
42 { 0x44f, 0x00 }, { 0x450, 0x00 }, { 0x451, 0xf0 }, { 0x452, 0x0f },
43 { 0x453, 0x00 }, { 0x456, 0x5e }, { 0x460, 0x66 }, { 0x461, 0x66 },
[all …]
/freebsd/sys/dev/rtwn/rtl8821a/
H A Dr21a_priv.h34 { 0x421, 0x0f }, { 0x428, 0x0a }, { 0x429, 0x10 }, { 0x430, 0x00 },
35 { 0x431, 0x00 }, { 0x432, 0x00 }, { 0x433, 0x01 }, { 0x434, 0x04 },
36 { 0x435, 0x05 }, { 0x436, 0x07 }, { 0x437, 0x08 }, { 0x43c, 0x04 },
37 { 0x43d, 0x05 }, { 0x43e, 0x07 }, { 0x43f, 0x08 }, { 0x440, 0x5d },
38 { 0x441, 0x01 }, { 0x442, 0x00 }, { 0x444, 0x10 }, { 0x445, 0x00 },
39 { 0x446, 0x00 }, { 0x447, 0x00 }, { 0x448, 0x00 }, { 0x449, 0xf0 },
40 { 0x44a, 0x0f }, { 0x44b, 0x3e }, { 0x44c, 0x10 }, { 0x44d, 0x00 },
41 { 0x44e, 0x00 }, { 0x44f, 0x00 }, { 0x450, 0x00 }, { 0x451, 0xf0 },
42 { 0x452, 0x0f }, { 0x453, 0x00 }, { 0x456, 0x5e }, { 0x460, 0x66 },
43 { 0x461, 0x66 }, { 0x4c8, 0x3f }, { 0x4c9, 0xff }, { 0x4cc, 0xff },
[all …]
/freebsd/sys/dev/rtwn/rtl8192c/
H A Dr92c_reg.h28 #define R92C_SYS_ISO_CTRL 0x000
29 #define R92C_SYS_FUNC_EN 0x002
30 #define R92C_APS_FSMCO 0x004
31 #define R92C_SYS_CLKR 0x008
32 #define R92C_AFE_MISC 0x010
33 #define R92C_SPS0_CTRL 0x011
34 #define R92C_SPS_OCP_CFG 0x018
35 #define R92C_RSV_CTRL 0x01c
36 #define R92C_RF_CTRL 0x01f
37 #define R92C_LDOA15_CTRL 0x020
[all …]
/freebsd/tools/tools/cxgbtool/
H A Dreg_defs.c7 { "SG_CONTROL", 0x0, 0 },
8 { "CmdQ0_Enable", 0, 1 },
24 { "SG_DOORBELL", 0x4, 0 },
25 { "CmdQ0_Enable", 0, 1 },
29 { "SG_CMD0BASELWR", 0x8, 0 },
30 { "SG_CMD0BASEUPR", 0xc, 0 },
31 { "SG_CMD1BASELWR", 0x10, 0 },
32 { "SG_CMD1BASEUPR", 0x14, 0 },
33 { "SG_FL0BASELWR", 0x18, 0 },
34 { "SG_FL0BASEUPR", 0x1c, 0 },
[all …]
/freebsd/sys/riscv/include/
H A Dencoding.h8 #define MATCH_BEQ 0x63
9 #define MASK_BEQ 0x707f
10 #define MATCH_BNE 0x1063
11 #define MASK_BNE 0x707f
12 #define MATCH_BLT 0x4063
13 #define MASK_BLT 0x707f
14 #define MATCH_BGE 0x5063
15 #define MASK_BGE 0x707f
16 #define MATCH_BLTU 0x6063
17 #define MASK_BLTU 0x707f
[all …]
/freebsd/sys/dev/rtwn/rtl8812a/
H A Dr12a_priv.h34 { 0x010, 0x0c },
37 { 0x025, 0x0f }, { 0x072, 0x00 }, { 0x420, 0x80 }, { 0x428, 0x0a }, \
38 { 0x429, 0x10 }, { 0x430, 0x00 }, { 0x431, 0x00 }, { 0x432, 0x00 }, \
39 { 0x433, 0x01 }, { 0x434, 0x04 }, { 0x435, 0x05 }, { 0x436, 0x07 }, \
40 { 0x437, 0x08 }, { 0x43c, 0x04 }, { 0x43d, 0x05 }, { 0x43e, 0x07 }, \
41 { 0x43f, 0x08 }, { 0x440, 0x5d }, { 0x441, 0x01 }, { 0x442, 0x00 }, \
42 { 0x444, 0x10 }, { 0x445, 0x00 }, { 0x446, 0x00 }, { 0x447, 0x00 }, \
43 { 0x448, 0x00 }, { 0x449, 0xf0 }, { 0x44a, 0x0f }, { 0x44b, 0x3e }, \
44 { 0x44c, 0x10 }, { 0x44d, 0x00 }, { 0x44e, 0x00 }, { 0x44f, 0x00 }, \
45 { 0x450, 0x00 }, { 0x451, 0xf0 }, { 0x452, 0x0f }, { 0x453, 0x00 }, \
[all …]
/freebsd/sys/dev/clk/allwinner/
H A Dccu_d1.c56 CCU_RESET(RST_MBUS, 0x540, 30)
57 CCU_RESET(RST_BUS_DE, 0x60C, 16)
58 CCU_RESET(RST_BUS_DI, 0x62C, 16)
59 CCU_RESET(RST_BUS_G2D, 0x63C, 16)
60 CCU_RESET(RST_BUS_CE, 0x68C, 16)
61 CCU_RESET(RST_BUS_VE, 0x69C, 16)
62 CCU_RESET(RST_BUS_DMA, 0x70C, 16)
63 CCU_RESET(RST_BUS_MSGBOX0, 0x71C, 16)
64 CCU_RESET(RST_BUS_MSGBOX1, 0x71C, 17)
65 CCU_RESET(RST_BUS_MSGBOX2, 0x71C, 18)
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsdm670.dtsi37 #clock-cells = <0>;
43 #clock-cells = <0>;
50 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0x0 0x0>;
59 qcom,freq-domain = <&cpufreq_hw 0>;
82 reg = <0x0 0x100>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
104 reg = <0x0 0x200>;
108 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
/freebsd/sys/dev/qat_c2xxx/
H A Dqatreg.h65 (((uintmax_t)(__n) >= NBBY * sizeof(uintmax_t)) ? 0 : \
75 #define MAX_NUM_AE 0x10
77 #define MAX_AE 0x18
81 #define MAX_USTORE_PER_SEG 0x8000 /* 16k * 2 */
98 #define INVLD_UWORD 0xffffffffffull /* invalid micro-instruction */
100 #define UWORD_MASK 0xbffffffffffull /* micro-word mask without parity */
102 #define AE_ALL_CTX 0xff
106 #define NO_REG_OFFSET 0
111 #define FUSECTL_REG 0x40
114 #define LEGFUSE_REG 0x4c
[all …]
/freebsd/contrib/llvm-project/llvm/lib/TargetParser/
H A DHost.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
82 // The cpu line is second (after the 'processor: 0' line), so if this in getHostCPUNameForPowerPC()
90 size_t CPULen = 0; in getHostCPUNameForPowerPC()
173 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { in getHostCPUNameForARM()
182 if (Implementer == "0x41") { // ARM Ltd. in getHostCPUNameForARM()
189 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The in getHostCPUNameForARM()
195 .Case("0x926", "arm926ej-s") in getHostCPUNameForARM()
196 .Case("0xb02", "mpcore") in getHostCPUNameForARM()
197 .Case("0xb36", "arm1136j-s") in getHostCPUNameForARM()
198 .Case("0xb56", "arm1156t2-s") in getHostCPUNameForARM()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.td3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
60 def BRC : CondBranchRI <"j#", 0xA74, z_br_ccmask>;
63 def BRCL : CondBranchRIL<"jg#", 0xC04>;
65 def BC : CondBranchRX<"b#", 0x47>;
66 def BCR : CondBranchRR<"b#r", 0x07>;
67 def BIC : CondBranchRXY<"bi#", 0xe347>,
74 def BRCAsm : AsmCondBranchRI <"brc", 0xA74>;
75 def BRCLAsm : AsmCondBranchRIL<"brcl", 0xC04>;
77 def BCAsm : AsmCondBranchRX<"bc", 0x47>;
78 def BCRAsm : AsmCondBranchRR<"bcr", 0x07>;
[all …]

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