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Searched +full:0 +full:xc03 (Results 1 – 21 of 21) sorted by relevance

/linux/Documentation/devicetree/bindings/media/
H A Dqcom,sdm660-camss.yaml109 port@0:
341 iommus = <&mmss_smmu 0xc00>,
342 <&mmss_smmu 0xc01>,
343 <&mmss_smmu 0xc02>,
344 <&mmss_smmu 0xc03>;
349 reg = <0x0ca00020 0x10>,
350 <0x0ca30000 0x100>,
351 <0x0ca30400 0x100>,
352 <0x0ca30800 0x100>,
353 <0x0ca30c00 0x100>,
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt76x0/
H A Dpci.c25 return 0; in mt76x0e_start()
35 0, 1000)) in mt76x0e_stop_hw()
42 0, 1000)) in mt76x0e_stop_hw()
105 if (err < 0) in mt76x0e_init_hardware()
110 if (err < 0) in mt76x0e_init_hardware()
115 if (err < 0) in mt76x0e_init_hardware()
120 if (mt76_chip(&dev->mt76) == 0x7610) { in mt76x0e_init_hardware()
123 mt76_clear(dev, MT_COEXCFG0, BIT(0)); in mt76x0e_init_hardware()
127 mt76_set(dev, MT_XO_CTRL7, 0xc03); in mt76x0e_init_hardware()
130 mt76_clear(dev, 0x110, BIT(9)); in mt76x0e_init_hardware()
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_4_d.h27 #define mmIH_VMID_0_LUT 0xe00
28 #define mmIH_VMID_1_LUT 0xe01
29 #define mmIH_VMID_2_LUT 0xe02
30 #define mmIH_VMID_3_LUT 0xe03
31 #define mmIH_VMID_4_LUT 0xe04
32 #define mmIH_VMID_5_LUT 0xe05
33 #define mmIH_VMID_6_LUT 0xe06
34 #define mmIH_VMID_7_LUT 0xe07
35 #define mmIH_VMID_8_LUT 0xe08
36 #define mmIH_VMID_9_LUT 0xe09
[all …]
H A Doss_3_0_1_d.h27 #define mmIH_VMID_0_LUT 0xe00
28 #define mmIH_VMID_1_LUT 0xe01
29 #define mmIH_VMID_2_LUT 0xe02
30 #define mmIH_VMID_3_LUT 0xe03
31 #define mmIH_VMID_4_LUT 0xe04
32 #define mmIH_VMID_5_LUT 0xe05
33 #define mmIH_VMID_6_LUT 0xe06
34 #define mmIH_VMID_7_LUT 0xe07
35 #define mmIH_VMID_8_LUT 0xe08
36 #define mmIH_VMID_9_LUT 0xe09
[all …]
H A Doss_2_0_d.h27 #define mmIH_VMID_0_LUT 0xf50
28 #define mmIH_VMID_1_LUT 0xf51
29 #define mmIH_VMID_2_LUT 0xf52
30 #define mmIH_VMID_3_LUT 0xf53
31 #define mmIH_VMID_4_LUT 0xf54
32 #define mmIH_VMID_5_LUT 0xf55
33 #define mmIH_VMID_6_LUT 0xf56
34 #define mmIH_VMID_7_LUT 0xf57
35 #define mmIH_VMID_8_LUT 0xf58
36 #define mmIH_VMID_9_LUT 0xf59
[all …]
H A Doss_3_0_d.h27 #define mmIH_VMID_0_LUT 0xe00
28 #define mmIH_VMID_1_LUT 0xe01
29 #define mmIH_VMID_2_LUT 0xe02
30 #define mmIH_VMID_3_LUT 0xe03
31 #define mmIH_VMID_4_LUT 0xe04
32 #define mmIH_VMID_5_LUT 0xe05
33 #define mmIH_VMID_6_LUT 0xe06
34 #define mmIH_VMID_7_LUT 0xe07
35 #define mmIH_VMID_8_LUT 0xe08
36 #define mmIH_VMID_9_LUT 0xe09
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Dintel_cx0_phy_regs.h30 #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A 0x64040
31 #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B 0x64140
32 #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1 0x16F240
33 #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2 0x16F440
45 … XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x1)
46 …ne XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x2)
47 #define XELPDP_PORT_M2P_COMMAND_READ REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x3)
51 #define XELPDP_PORT_M2P_ADDRESS_MASK REG_GENMASK(11, 0)
65 #define XELPDP_PORT_P2M_COMMAND_READ_ACK 0x4
66 #define XELPDP_PORT_P2M_COMMAND_WRITE_ACK 0x5
[all …]
/linux/arch/riscv/include/asm/
H A Dcsr.h13 #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */
14 #define SR_MIE _AC(0x00000008, UL) /* Machine Interrupt Enable */
15 #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */
16 #define SR_MPIE _AC(0x00000080, UL) /* Previous Machine IE */
17 #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */
18 #define SR_MPP _AC(0x00001800, UL) /* Previously Machine */
19 #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */
21 #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */
22 #define SR_FS_OFF _AC(0x00000000, UL)
23 #define SR_FS_INITIAL _AC(0x00002000, UL)
[all …]
/linux/tools/arch/riscv/include/asm/
H A Dcsr.h12 #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */
13 #define SR_MIE _AC(0x00000008, UL) /* Machine Interrupt Enable */
14 #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */
15 #define SR_MPIE _AC(0x00000080, UL) /* Previous Machine IE */
16 #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */
17 #define SR_MPP _AC(0x00001800, UL) /* Previously Machine */
18 #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */
20 #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */
21 #define SR_FS_OFF _AC(0x00000000, UL)
22 #define SR_FS_INITIAL _AC(0x00002000, UL)
[all …]
/linux/drivers/slimbus/
H A Dstream.c19 * @segdist_code: Segment Distribution Code SD[11:0]
20 * @seg_offset_mask: Segment offset mask in SD[11:0]
32 {1, 1536, 0x200, 0xdff},
33 {2, 768, 0x100, 0xcff},
34 {4, 384, 0x080, 0xc7f},
35 {8, 192, 0x040, 0xc3f},
36 {16, 96, 0x020, 0xc1f},
37 {32, 48, 0x010, 0xc0f},
38 {64, 24, 0x008, 0xc07},
39 {128, 12, 0x004, 0xc03},
[all …]
/linux/drivers/media/pci/ivtv/
H A Divtv-cards.c36 .demod = { 0x43, I2C_CLIENT_END },
37 .tv = { 0x61, 0x60, I2C_CLIENT_END },
42 .radio = { 0x60, I2C_CLIENT_END },
43 .demod = { 0x43, I2C_CLIENT_END },
44 .tv = { 0x61, I2C_CLIENT_END },
51 .tv = { 0x4b, I2C_CLIENT_END },
58 must be added under vendor 0x4444 (Conexant) as subsystem IDs.
74 { IVTV_CARD_INPUT_VID_TUNER, 0, IVTV_SAA71XX_COMPOSITE4 },
98 .video_output = 0,
130 { IVTV_CARD_INPUT_VID_TUNER, 0, IVTV_SAA71XX_COMPOSITE4 },
[all …]
/linux/drivers/media/platform/chips-media/coda/
H A Dcoda-jpeg.c26 #define SOI_MARKER 0xffd8
27 #define APP9_MARKER 0xffe9
28 #define DRI_MARKER 0xffdd
29 #define DQT_MARKER 0xffdb
30 #define DHT_MARKER 0xffc4
31 #define SOF_MARKER 0xffc0
32 #define SOS_MARKER 0xffda
33 #define EOI_MARKER 0xffd9
64 0x00, 0x01, 0x05, 0x01, 0x01, 0x01, 0x01, 0x01,
65 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
[all …]
/linux/drivers/net/ethernet/intel/i40e/
H A Di40e_register.h11 #define I40E_GL_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_GL_ATQLEN_ATQCRIT_SHIFT)
12 #define I40E_PF_ARQBAH 0x00080180 /* Reset: EMPR */
13 #define I40E_PF_ARQBAL 0x00080080 /* Reset: EMPR */
14 #define I40E_PF_ARQH 0x00080380 /* Reset: EMPR */
15 #define I40E_PF_ARQH_ARQH_SHIFT 0
16 #define I40E_PF_ARQH_ARQH_MASK I40E_MASK(0x3FF, I40E_PF_ARQH_ARQH_SHIFT)
17 #define I40E_PF_ARQLEN 0x00080280 /* Reset: EMPR */
19 #define I40E_PF_ARQLEN_ARQVFE_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQVFE_SHIFT)
21 #define I40E_PF_ARQLEN_ARQOVFL_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQOVFL_SHIFT)
23 #define I40E_PF_ARQLEN_ARQCRIT_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQCRIT_SHIFT)
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsdm630.dtsi35 #clock-cells = <0>;
42 #clock-cells = <0>;
50 #size-cells = <0>;
55 reg = <0x0 0x100>;
75 reg = <0x0 0x101>;
90 reg = <0x0 0x102>;
105 reg = <0x0 0x103>;
117 CPU4: cpu@0 {
120 reg = <0x0 0x0>;
140 reg = <0x0 0x1>;
[all …]
/linux/include/linux/mfd/madera/
H A Dregisters.h14 #define MADERA_SOFTWARE_RESET 0x00
15 #define MADERA_HARDWARE_REVISION 0x01
16 #define MADERA_CTRL_IF_CFG_1 0x08
17 #define MADERA_CTRL_IF_CFG_2 0x09
18 #define MADERA_CTRL_IF_CFG_3 0x0A
19 #define MADERA_WRITE_SEQUENCER_CTRL_0 0x16
20 #define MADERA_WRITE_SEQUENCER_CTRL_1 0x17
21 #define MADERA_WRITE_SEQUENCER_CTRL_2 0x18
22 #define MADERA_TONE_GENERATOR_1 0x20
23 #define MADERA_TONE_GENERATOR_2 0x21
[all …]
/linux/sound/soc/codecs/
H A Dwm5100.h26 #define WM5100_CLKSRC_MCLK1 0
34 #define WM5100_CLKSRC_ASYNCCLK 0x100
39 #define WM5100_FLL_SRC_MCLK1 0x0
40 #define WM5100_FLL_SRC_MCLK2 0x1
41 #define WM5100_FLL_SRC_FLL1 0x4
42 #define WM5100_FLL_SRC_FLL2 0x5
43 #define WM5100_FLL_SRC_AIF1BCLK 0x8
44 #define WM5100_FLL_SRC_AIF2BCLK 0x9
45 #define WM5100_FLL_SRC_AIF3BCLK 0xa
50 #define WM5100_SOFTWARE_RESET 0x00
[all …]
/linux/drivers/mfd/
H A Dcs47l90-tables.c18 { 0x8A, 0x5555 },
19 { 0x8A, 0xAAAA },
20 { 0x4CF, 0x0700 },
21 { 0x171, 0x0003 },
22 { 0x101, 0x0444 },
23 { 0x159, 0x0002 },
24 { 0x120, 0x0444 },
25 { 0x1D1, 0x0004 },
26 { 0x1E0, 0xC084 },
27 { 0x159, 0x0000 },
[all …]
H A Dcs47l85-tables.c18 { 0x80, 0x0003 },
19 { 0x213, 0x03E4 },
20 { 0x177, 0x0281 },
21 { 0x197, 0x0281 },
22 { 0x1B7, 0x0281 },
23 { 0x4B1, 0x010A },
24 { 0x4CF, 0x0933 },
25 { 0x36C, 0x011B },
26 { 0x4B8, 0x1120 },
27 { 0x4A0, 0x3280 },
[all …]
/linux/include/linux/mfd/arizona/
H A Dregisters.h16 #define ARIZONA_SOFTWARE_RESET 0x00
17 #define ARIZONA_DEVICE_REVISION 0x01
18 #define ARIZONA_CTRL_IF_SPI_CFG_1 0x08
19 #define ARIZONA_CTRL_IF_I2C1_CFG_1 0x09
20 #define ARIZONA_CTRL_IF_I2C2_CFG_1 0x0A
21 #define ARIZONA_CTRL_IF_I2C1_CFG_2 0x0B
22 #define ARIZONA_CTRL_IF_I2C2_CFG_2 0x0C
23 #define ARIZONA_CTRL_IF_STATUS_1 0x0D
24 #define ARIZONA_WRITE_SEQUENCER_CTRL_0 0x16
25 #define ARIZONA_WRITE_SEQUENCER_CTRL_1 0x17
[all …]
/linux/drivers/net/ethernet/sfc/siena/
H A Dmcdi_pcol.h36 #define MC_SMEM_P0_DOORBELL_OFST 0x000
37 #define MC_SMEM_P1_DOORBELL_OFST 0x004
39 #define MC_SMEM_P0_PDU_OFST 0x008
40 #define MC_SMEM_P1_PDU_OFST 0x108
41 #define MC_SMEM_PDU_LEN 0x100
42 #define MC_SMEM_P0_PTP_TIME_OFST 0x7f0
43 #define MC_SMEM_P0_STATUS_OFST 0x7f8
44 #define MC_SMEM_P1_STATUS_OFST 0x7fc
48 #define MC_STATUS_DWORD_REBOOT (0xb007b007)
49 #define MC_STATUS_DWORD_ASSERT (0xdeaddead)
[all …]
/linux/drivers/net/ethernet/sfc/
H A Dmcdi_pcol.h36 #define MC_SMEM_P0_DOORBELL_OFST 0x000
37 #define MC_SMEM_P1_DOORBELL_OFST 0x004
39 #define MC_SMEM_P0_PDU_OFST 0x008
40 #define MC_SMEM_P1_PDU_OFST 0x108
41 #define MC_SMEM_PDU_LEN 0x100
42 #define MC_SMEM_P0_PTP_TIME_OFST 0x7f0
43 #define MC_SMEM_P0_STATUS_OFST 0x7f8
44 #define MC_SMEM_P1_STATUS_OFST 0x7fc
48 #define MC_STATUS_DWORD_REBOOT (0xb007b007)
49 #define MC_STATUS_DWORD_ASSERT (0xdeaddead)
[all …]