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Searched +full:0 +full:xc03 (Results 1 – 7 of 7) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dqcom,sdm660-camss.yaml109 port@0:
341 iommus = <&mmss_smmu 0xc00>,
342 <&mmss_smmu 0xc01>,
343 <&mmss_smmu 0xc02>,
344 <&mmss_smmu 0xc03>;
349 reg = <0x0ca00020 0x10>,
350 <0x0ca30000 0x100>,
351 <0x0ca30400 0x100>,
352 <0x0ca30800 0x100>,
353 <0x0ca30c00 0x100>,
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/freebsd/sys/contrib/dev/mediatek/mt76/mt76x0/
H A Dpci.c25 return 0; in mt76x0e_start()
35 0, 1000)) in mt76x0e_stop_hw()
42 0, 1000)) in mt76x0e_stop_hw()
101 if (err < 0) in mt76x0e_init_hardware()
106 if (err < 0) in mt76x0e_init_hardware()
111 if (err < 0) in mt76x0e_init_hardware()
116 if (mt76_chip(&dev->mt76) == 0x7610) { in mt76x0e_init_hardware()
119 mt76_clear(dev, MT_COEXCFG0, BIT(0)); in mt76x0e_init_hardware()
123 mt76_set(dev, MT_XO_CTRL7, 0xc03); in mt76x0e_init_hardware()
126 mt76_clear(dev, 0x110, BIT(9)); in mt76x0e_init_hardware()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMSystemRegister.td3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
40 let M2M3Encoding8{7-0} = Enc12{7-0};
47 def : MClassSysReg<0, 0, 0, 0x400, "apsr_g">;
48 def : MClassSysReg<0, 1, 1, 0xc00, "apsr_nzcvqg">;
49 def : MClassSysReg<0, 0, 0, 0x401, "iapsr_g">;
50 def : MClassSysReg<0, 1, 1, 0xc01, "iapsr_nzcvqg">;
51 def : MClassSysReg<0, 0, 0, 0x402, "eapsr_g">;
52 def : MClassSysReg<0, 1, 1, 0xc02, "eapsr_nzcvqg">;
53 def : MClassSysReg<0, 0, 0, 0x403, "xpsr_g">;
54 def : MClassSysReg<0, 1, 1, 0xc03, "xpsr_nzcvqg">;
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSystemOperands.td3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
30 // Privilege Access: Read and Write = 0, 1, 2; Read-Only = 3.
31 // Privilege Mode: User = 0, System = 1 or Machine = 3.
37 // bits<6> Number = op{5 - 0};
39 bit isRV32Only = 0;
78 def SysRegFFLAGS : SysReg<"fflags", 0x001>;
79 def SysRegFRM : SysReg<"frm", 0x002>;
80 def SysRegFCSR : SysReg<"fcsr", 0x003>;
85 def CYCLE : SysReg<"cycle", 0xC00>;
86 def TIME : SysReg<"time", 0xC01>;
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/freebsd/sys/riscv/include/
H A Dencoding.h8 #define MATCH_BEQ 0x63
9 #define MASK_BEQ 0x707f
10 #define MATCH_BNE 0x1063
11 #define MASK_BNE 0x707f
12 #define MATCH_BLT 0x4063
13 #define MASK_BLT 0x707f
14 #define MATCH_BGE 0x5063
15 #define MASK_BGE 0x707f
16 #define MATCH_BLTU 0x6063
17 #define MASK_BLTU 0x707f
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/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsdm630.dtsi35 #clock-cells = <0>;
42 #clock-cells = <0>;
50 #size-cells = <0>;
55 reg = <0x0 0x100>;
75 reg = <0x0 0x101>;
90 reg = <0x0 0x102>;
105 reg = <0x0 0x103>;
117 CPU4: cpu@0 {
120 reg = <0x0 0x0>;
140 reg = <0x0 0x1>;
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/freebsd/sys/dev/sfxge/common/
H A Defx_regs_mcdi.h55 #define MC_SMEM_P0_DOORBELL_OFST 0x000
56 #define MC_SMEM_P1_DOORBELL_OFST 0x004
58 #define MC_SMEM_P0_PDU_OFST 0x008
59 #define MC_SMEM_P1_PDU_OFST 0x108
60 #define MC_SMEM_PDU_LEN 0x100
61 #define MC_SMEM_P0_PTP_TIME_OFST 0x7f0
62 #define MC_SMEM_P0_STATUS_OFST 0x7f8
63 #define MC_SMEM_P1_STATUS_OFST 0x7fc
67 #define MC_STATUS_DWORD_REBOOT (0xb007b007)
68 #define MC_STATUS_DWORD_ASSERT (0xdeaddead)
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