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/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Driscv,aplic.yaml74 first child APLIC domain assigned child index 0. The APLIC domain child
122 reg = <0xc000000 0x4080>;
134 reg = <0xd000000 0x4080>;
144 reg = <0xe000000 0x4080>;
156 reg = <0xc000000 0x4000>;
167 reg = <0xd000000 0x4000>;
H A Dsifive,plic-1.0.0.txt26 "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
31 - compatible : "sifive,plic-1.0.0" and a string identifying the actual
33 - #address-cells : should be <0> or more.
46 #address-cells = <0>;
48 compatible = "sifive,plic-1.0.0", "sifive,fu540-c000-plic";
56 reg = <0xc000000 0x4000000>;
H A Dsifive,plic-1.0.0.yaml5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
39 "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
43 The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the
64 - const: sifive,plic-1.0.0
75 - const: sifive,plic-1.0.0
84 const: 0
164 #address-cells = <0>;
166 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
173 reg = <0xc000000 0x4000000>;
/freebsd/sys/contrib/device-tree/src/riscv/kendryte/
H A Dk210.dtsi29 #size-cells = <0>;
31 cpu0: cpu@0 {
33 reg = <0>;
37 i-cache-size = <0x8000>;
39 d-cache-size = <0x8000>;
55 i-cache-size = <0x8000>;
57 d-cache-size = <0x8000>;
71 reg = <0x80000000 0x400000>,
72 <0x80400000 0x200000>,
73 <0x80600000 0x200000>;
[all …]
/freebsd/sys/dts/arm/
H A Dqcom-ipq4019-ethernet.dtsi34 #size-cells = <0>;
36 reg = <0x90000 0x64>;
42 reg = <0xc000000 0x80000>;
50 * facing. It's almost always going to be port 0
51 * (ie bit 0.)
53 switch_cpu_bmp = <0x1>;
60 switch_lan_bmp = <0x1e>;
67 switch_wan_bmp = <0x20>;
76 switch_mac_mode = <0>;
82 reg = <0x98000 0x800>;
[all …]
/freebsd/sys/contrib/device-tree/src/mips/ralink/
H A Dmt7628a.dtsi10 #size-cells = <0>;
12 cpu@0 {
15 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10000000 0x200000>;
34 ranges = <0x0 0x10000000 0x1FFFFF>;
39 sysc: system-controller@0 {
41 reg = <0x0 0x60>;
46 reg = <0x60 0x8>;
48 #size-cells = <0>;
[all …]
/freebsd/crypto/openssl/doc/man3/
H A DOPENSSL_s390xcap.pod61 The 64-bit masks are specified in hexadecimal notation. The 0x prefix is
66 column are consistent with [1], that is, 0 denotes the leftmost bit and
192 OPENSSL_s390xcap="stfle:~0:~0:~0x4000000000000000"
196 OPENSSL_s390xcap="km:~0x2800:~0;kimd:~0xc000000:~0"
/freebsd/secure/lib/libcrypto/man/man3/
H A DOPENSSL_s390xcap.333 .\" If the F register is >0, we'll generate index entries on stderr for
41 .nr rF 0
49 . nr % 0
114 The 64\-bit masks are specified in hexadecimal notation. The 0x prefix is
119 column are consistent with [1], that is, 0 denotes the leftmost bit and
248 \& OPENSSL_s390xcap="stfle:~0:~0:~0x4000000000000000"
254 \& OPENSSL_s390xcap="km:~0x2800:~0;kimd:~0xc000000:~0"
/freebsd/sys/contrib/device-tree/src/arm/microchip/
H A Dat91sam9m10g45ek.dts22 reg = <0x70000000 0x4000000>;
42 timer@0 {
44 reg = <0>, <1>;
54 pinctrl-0 =
70 reg = <0x30>;
72 pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>;
98 pinctrl-0 = <
104 slot@0 {
105 reg = <0>;
[all...]
/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_unit_adapter_regs.h44 #define AL_PCI_COMMAND 0x04 /* 16 bits */
45 #define AL_PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
46 #define AL_PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
47 #define AL_PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
49 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */
51 #define AL_PCI_BASE_ADDRESS_SPACE_IO 0x01
52 #define AL_PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
53 #define AL_PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
54 #define AL_PCI_BASE_ADDRESS_DEVICE_ID 0x0c
56 #define AL_PCI_BASE_ADDRESS_0 0x10
[all …]
/freebsd/sys/contrib/device-tree/src/riscv/sifive/
H A Dfu540-c000.dtsi24 #size-cells = <0>;
25 cpu0: cpu@0 {
31 reg = <0>;
182 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
183 reg = <0x0 0xc000000 0x0 0x4000000>;
184 #address-cells = <0>;
[all...]
H A Dfu740-c000.dtsi24 #size-cells = <0>;
25 cpu0: cpu@0 {
32 reg = <0x0>;
59 reg = <0x1>;
86 reg = <0x2>;
113 reg = <0x3>;
140 reg = <0x4>;
184 #address-cells = <0>;
185 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
186 reg = <0x
[all...]
/freebsd/sys/contrib/device-tree/src/riscv/starfive/
H A Djh7100.dtsi18 #size-cells = <0>;
20 U74_0: cpu@0 {
22 reg = <0>;
118 #clock-cells = <0>;
121 clock-frequency = <0>;
126 #clock-cells = <0>;
129 clock-frequency = <0>;
134 #clock-cells = <0>;
137 clock-frequency = <0>;
142 #clock-cells = <0>;
[all …]
H A Djh7110.dtsi20 #size-cells = <0>;
22 S7_0: cpu@0 {
24 reg = <0>;
200 cpu_opp: opp-table-0 {
260 #clock-cells = <0>;
265 #clock-cells = <0>;
271 #clock-cells = <0>;
277 #clock-cells = <0>;
283 #clock-cells = <0>;
289 #clock-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/wireless/
H A Dqcom,ath11k.yaml270 reg = <0xc000000 0x2000000>;
271 interrupts = <0 320 1>,
272 <0 319 1>,
273 <0 318 1>,
274 <0 317 1>,
275 <0 316 1>,
276 <0 315 1>,
277 <0 314 1>,
278 <0 311 1>,
279 <0 310 1>,
[all …]
/freebsd/sys/contrib/device-tree/src/riscv/microchip/
H A Dmicrochip-mpfs.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
24 reg = <0>;
146 #clock-cells = <0>;
157 reg = <0x0 0x2010000 0x0 0x1000>;
169 reg = <0x0 0x2000000 0x0 0xC000>;
178 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
179 reg = <0x0 0xc000000 0x0 0x4000000>;
180 #address-cells = <0>;
193 reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
[all …]
H A Dmpfs.dtsi15 #size-cells = <0>;
18 cpu0: cpu@0 {
24 reg = <0>;
189 #clock-cells = <0>;
194 mboxes = <&mbox 0>;
199 #clock-cells = <0>;
211 reg = <0x0 0x2010000 0x0 0x1000>;
223 reg = <0x0 0x2000000 0x0 0xC000>;
232 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
233 reg = <0x0 0xc000000 0x0 0x4000000>;
[all …]
/freebsd/crypto/krb5/src/plugins/preauth/spake/
H A Dedwards25519_fiat.h12 /* carry_chain = [0, 1, 2, 3, 4, 0, 1] */
13 /* eval z = z[0] + (z[1] << 51) + (z[2] << 102) + (z[3] << 153) + (z[4] << 204) */
14 /* bytes_eval z = z[0] + (z[1] << 8) + (z[2] << 16) + (z[3] << 24) + (z[4] << 32) + (z[5] << 40) …
15 /* balance = [0xfffffffffffda, 0xffffffffffffe, 0xffffffffffffe, 0xffffffffffffe, 0xffffffffffffe…
32 /* Bounds: [[0x0 ~> 0x18000000000000], [0x0 ~> 0x18000000000000], [0x0 ~> 0x18000000000000], [0x0 ~…
36 /* Bounds: [[0x0 ~> 0x8000000000000], [0x0 ~> 0x8000000000000], [0x0 ~> 0x8000000000000], [0x0 ~> 0…
61 * arg1: [0x0 ~> 0x1]
62 * arg2: [0x0 ~> 0x7ffffffffffff]
63 * arg3: [0x0 ~> 0x7ffffffffffff]
65 * out1: [0x0 ~> 0x7ffffffffffff]
[all …]
/freebsd/sys/contrib/device-tree/src/riscv/canaan/
H A Dk210.dtsi27 #size-cells = <0>;
29 cpu0: cpu@0 {
32 reg = <0>;
36 i-cache-size = <0x8000>;
38 d-cache-size = <0x8000>;
52 i-cache-size = <0x8000>;
54 d-cache-size = <0x8000>;
77 reg = <0x80000000 0x400000>, /* sram0 4 MiB */
78 <0x80400000 0x200000>, /* sram1 2 MiB */
79 <0x80600000 0x200000>; /* aisram 2 MiB */
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-j7200-main.dtsi10 #clock-cells = <0>;
18 reg = <0x00 0x70000000 0x00 0x100000>;
21 ranges = <0x00 0x00 0x70000000 0x100000>;
23 atf-sram@0 {
24 reg = <0x00 0x20000>;
30 reg = <0x00 0x00100000 0x00 0x1c000>;
33 ranges = <0x00 0x00 0x00100000 0x1c000>;
37 reg = <0x4080 0x20>;
39 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
40 <0x8 0x3>, <0xc 0x3>; /* SERDES0 lane2/3 select */
[all …]
H A Dk3-j784s4-main.dtsi16 #clock-cells = <0>;
26 reg = <0x00 0x70000000 0x00 0x800000>;
29 ranges = <0x00 0x00 0x70000000 0x800000>;
31 atf-sram@0 {
32 reg = <0x00 0x20000>;
36 reg = <0x1f0000 0x10000>;
40 reg = <0x200000 0x200000>;
46 reg = <0x00 0x00100000 0x00 0x1c000>;
49 ranges = <0x00 0x00 0x00100000 0x1c000>;
53 reg = <0x4034 0x4>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-ls1088a.dtsi27 #size-cells = <0>;
30 cpu0: cpu@0 {
33 reg = <0x0>;
34 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
42 reg = <0x1>;
43 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
51 reg = <0x2>;
52 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
60 reg = <0x3>;
61 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
[all …]
H A Dfsl-ls208xa.dtsi33 #size-cells = <0>;
38 reg = <0x00000000 0x80000000 0 0x80000000>;
44 #clock-cells = <0>;
51 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
52 <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
53 <0x0 0x0c0c0000 0 0x2000>, /* GICC */
54 <0x0 0x0c0d0000 0 0x1000>, /* GICH */
55 <0x0 0x0c0e0000 0 0x20000>; /* GICV */
67 reg = <0x0 0x6020000 0 0x20000>;
73 reg = <0x0 0x1e60000 0x0 0x4>;
[all …]
H A Dfsl-ls1028a.dtsi23 #size-cells = <0>;
25 cpu0: cpu@0 {
28 reg = <0x0>;
30 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
31 i-cache-size = <0xc000>;
34 d-cache-size = <0x8000>;
45 reg = <0x1>;
47 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
48 i-cache-size = <0xc000>;
51 d-cache-size = <0x8000>;
[all …]
/freebsd/tests/sys/cddl/zfs/tests/txg_integrity/
H A Dtxg_integrity.c84 #define USE_MMAP 0
90 //partitions[-1] is understood to be 0 and partitions[NUM_CHUNKS] must be 1.0
94 //8 / (NUM_CHUNKS * CLUSTERSIZE) = 1 / 524288 = 0x0.00002
98 //chunk 0 corresponds to bit 1, chunk 1 to bit 2, etc
106 if (chunk == 0){ in get_chunk_range()
107 *begin = 0; in get_chunk_range()
117 leader_syncs = 0,
125 {0x2000000, 0x4000000, 0x6000000, 0x8000000, 0xa000000, 0xc000000, 0xe000000, 0x10000000,
126 0x12000000, 0x14000000, 0x16000000, 0x18000000, 0x1a000000, 0x1c000000, 0x1e000000, 0x20000000,
127 0x22000000, 0x24000000, 0x26000000, 0x28000000, 0x2a000000, 0x2c000000, 0x2e000000, 0x30000000,
[all …]

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