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/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_dump.h22 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
23 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
24 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
25 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
45 #define BNX2X_DUMP_VERSION 0x61111111
65 static const u32 page_vals_e2[] = {0, 128};
68 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
74 static const u32 page_vals_e3[] = {0, 128};
77 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
81 { 0x2000, 1, 0x1f, 0xfff},
[all …]
/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt2712.c20 MTK_PIN_PUPD_SPEC_SR(18, 0xe50, 2, 1, 0),
21 MTK_PIN_PUPD_SPEC_SR(19, 0xe60, 12, 11, 10),
22 MTK_PIN_PUPD_SPEC_SR(20, 0xe50, 5, 4, 3),
23 MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 15, 14, 13),
24 MTK_PIN_PUPD_SPEC_SR(22, 0xe50, 8, 7, 6),
25 MTK_PIN_PUPD_SPEC_SR(23, 0xe70, 2, 1, 0),
27 MTK_PIN_PUPD_SPEC_SR(30, 0xf30, 2, 1, 0),
28 MTK_PIN_PUPD_SPEC_SR(31, 0xf30, 6, 5, 4),
29 MTK_PIN_PUPD_SPEC_SR(32, 0xf30, 10, 9, 8),
30 MTK_PIN_PUPD_SPEC_SR(33, 0xf30, 14, 13, 12),
[all …]
H A Dpinctrl-mt8127.c19 /* 0E4E8SR 4/8/12/16 */
21 /* 0E2E4SR 2/4/6/8 */
24 MTK_DRV_GRP(2, 16, 0, 2, 2)
28 MTK_PIN_DRV_GRP(0, 0xb00, 0, 1),
29 MTK_PIN_DRV_GRP(1, 0xb00, 0, 1),
30 MTK_PIN_DRV_GRP(2, 0xb00, 0, 1),
31 MTK_PIN_DRV_GRP(3, 0xb00, 0, 1),
32 MTK_PIN_DRV_GRP(4, 0xb00, 0, 1),
33 MTK_PIN_DRV_GRP(5, 0xb00, 0, 1),
34 MTK_PIN_DRV_GRP(6, 0xb00, 0, 1),
[all …]
H A Dpinctrl-mt8173.c18 #define DRV_BASE 0xb00
21 MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 2, 1, 0), /* KROW0 */
22 MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 6, 5, 4), /* KROW1 */
23 MTK_PIN_PUPD_SPEC_SR(121, 0xe00, 10, 9, 8), /* KROW2 */
24 MTK_PIN_PUPD_SPEC_SR(122, 0xe10, 2, 1, 0), /* KCOL0 */
25 MTK_PIN_PUPD_SPEC_SR(123, 0xe10, 6, 5, 4), /* KCOL1 */
26 MTK_PIN_PUPD_SPEC_SR(124, 0xe10, 10, 9, 8), /* KCOL2 */
28 MTK_PIN_PUPD_SPEC_SR(67, 0xd10, 2, 1, 0), /* ms0 DS */
29 MTK_PIN_PUPD_SPEC_SR(68, 0xd00, 2, 1, 0), /* ms0 RST */
30 MTK_PIN_PUPD_SPEC_SR(66, 0xc10, 2, 1, 0), /* ms0 cmd */
[all …]
/linux/Documentation/devicetree/bindings/fsi/
H A Dfsi.txt57 #size-cells = <0>;
89 chip-id = <0>;
98 For example, for a slave using a single 0x400-byte page starting at address
99 0xc00:
102 reg = <0xc00 0x400>;
125 #size-cells = <0>;
127 /* A FSI slave (aka. CFAM) at link 0, ID 0. */
128 cfam@0,0 {
129 reg = <0 0>;
132 chip-id = <0>;
[all …]
/linux/include/uapi/linux/
H A Dadfs_fs.h9 * Disc Record at disc address 0xc00
40 #define ADFS_DISCRECORD (0xc00)
41 #define ADFS_DR_OFFSET (0x1c0)
/linux/arch/mips/boot/dts/ralink/
H A Dmt7628a.dtsi10 #size-cells = <0>;
12 cpu@0 {
15 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10000000 0x200000>;
34 ranges = <0x0 0x10000000 0x1FFFFF>;
39 sysc: system-controller@0 {
41 reg = <0x0 0x60>;
46 reg = <0x60 0x8>;
48 #size-cells = <0>;
[all …]
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,nvic.txt22 This is at a fixed address (0xe000e100) and size (0xc00).
34 reg = <0xe000e100 0xc00>;
/linux/drivers/staging/media/meson/vdec/
H A Dvdec_hevc.c19 #define AO_RTI_GEN_PWR_SLEEP0 0xe8
20 #define AO_RTI_GEN_PWR_ISO0 0xec
38 if (ret < 0) { in vdec_hevc_load_firmware()
59 amvdec_write_dos(core, HEVC_MPSR, 0); in vdec_hevc_load_firmware()
60 amvdec_write_dos(core, HEVC_CPSR, 0); in vdec_hevc_load_firmware()
64 amvdec_write_dos(core, HEVC_IMEM_DMA_CTRL, (0x8000 | (7 << 16))); in vdec_hevc_load_firmware()
66 while (i && (readl(core->dos_base + HEVC_IMEM_DMA_CTRL) & 0x8000)) in vdec_hevc_load_firmware()
69 if (i == 0) { in vdec_hevc_load_firmware()
119 amvdec_write_dos(core, HEVC_ASSIST_MBOX1_MASK, 0); in __vdec_hevc_stop()
121 amvdec_write_dos(core, HEVC_MPSR, 0); in __vdec_hevc_stop()
[all …]
/linux/drivers/pinctrl/samsung/
H A Dpinctrl-exynos-arm.c27 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
32 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
36 #define S5P_OTHERS 0xE000
43 #define S5P_PIN_PULL_DISABLE 0
86 clk_base = of_iomap(np, 0); in s5pv210_retention_init()
106 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
107 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
108 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
109 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
110 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
[all …]
/linux/arch/powerpc/kvm/
H A Dbook3s_64_entry.S27 * anything here, but the 0xc00 handler has already clobbered CTR
44 li r10,0xc00
76 cmpdi r10,0x200
133 * MSR[DR]=1 while leaving MSR[IR]=0, so it continues to fetch HV instructions
156 cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE | 0x2
186 * Enter the guest on a ISAv3.0 or later system.
232 cmpdi r4,0
280 li r10,0xc00
369 li r10,0
H A Dtrace_book3s.h10 {0x100, "SYSTEM_RESET"}, \
11 {0x200, "MACHINE_CHECK"}, \
12 {0x300, "DATA_STORAGE"}, \
13 {0x380, "DATA_SEGMENT"}, \
14 {0x400, "INST_STORAGE"}, \
15 {0x480, "INST_SEGMENT"}, \
16 {0x500, "EXTERNAL"}, \
17 {0x502, "EXTERNAL_HV"}, \
18 {0x600, "ALIGNMENT"}, \
19 {0x700, "PROGRAM"}, \
[all …]
/linux/arch/arm/boot/dts/
H A Darmv7-m.dtsi7 reg = <0xe000e100 0xc00>;
12 reg = <0xe000e010 0x10>;
/linux/arch/arm/mach-omap2/
H A Domap-wakeupgen.h12 #define OMAP_WKUPGEN_BASE 0x48281000
14 #define OMAP_WKG_CONTROL_0 0x00
15 #define OMAP_WKG_ENB_A_0 0x10
16 #define OMAP_WKG_ENB_B_0 0x14
17 #define OMAP_WKG_ENB_C_0 0x18
18 #define OMAP_WKG_ENB_D_0 0x1c
19 #define OMAP_WKG_ENB_E_0 0x20
20 #define OMAP_WKG_ENB_A_1 0x410
21 #define OMAP_WKG_ENB_B_1 0x414
22 #define OMAP_WKG_ENB_C_1 0x418
[all …]
/linux/tools/perf/arch/powerpc/util/
H A Dbook3s_hv_exits.h10 {0x0, "RETURN_TO_HOST"}, \
11 {0x100, "SYSTEM_RESET"}, \
12 {0x200, "MACHINE_CHECK"}, \
13 {0x300, "DATA_STORAGE"}, \
14 {0x380, "DATA_SEGMENT"}, \
15 {0x400, "INST_STORAGE"}, \
16 {0x480, "INST_SEGMENT"}, \
17 {0x500, "EXTERNAL"}, \
18 {0x502, "EXTERNAL_HV"}, \
19 {0x600, "ALIGNMENT"}, \
[all …]
/linux/drivers/media/platform/mediatek/mdp3/
H A Dmdp_reg_color.h10 #define MDP_COLOR_WIN_X_MAIN (0x40C)
11 #define MDP_COLOR_WIN_Y_MAIN (0x410)
12 #define MDP_COLOR_START (0xC00)
13 #define MDP_COLOR_INTEN (0xC04)
14 #define MDP_COLOR_OUT_SEL (0xC0C)
15 #define MDP_COLOR_INTERNAL_IP_WIDTH (0xC50)
16 #define MDP_COLOR_INTERNAL_IP_HEIGHT (0xC54)
17 #define MDP_COLOR_CM1_EN (0xC60)
18 #define MDP_COLOR_CM2_EN (0xCA0)
21 #define MDP_COLOR_WIN_X_MAIN_MASK (0xFFFFFFFF)
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_4_1_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x2
36 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1
[all …]
/linux/Documentation/devicetree/bindings/reset/
H A Dsophgo,sg2042-reset.yaml33 reg = <0xc00 0xc>;
H A Dbitmain,bm1880-reset.yaml34 reg = <0xc00 0x8>;
/linux/arch/arm/mach-imx/
H A Dheadsmp.S21 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
26 mrc p15, 0, r0, c0, c0, 0
29 /* 0xc07 is cortex A7's ID */
30 mov r1, #0xc00
31 orr r1, #0x7
/linux/drivers/bus/
H A Domap_l3_noc.h16 #define CUSTOM_ERROR 0x2
17 #define STANDARD_ERROR 0x0
18 #define INBAND_ERROR 0x0
19 #define L3_APPLICATION_ERROR 0x0
20 #define L3_DEBUG_ERROR 0x1
23 #define L3_TARG_STDERRLOG_MAIN 0x48
24 #define L3_TARG_STDERRLOG_HDR 0x4c
25 #define L3_TARG_STDERRLOG_MSTADDR 0x50
26 #define L3_TARG_STDERRLOG_INFO 0x58
27 #define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c
[all …]
/linux/Documentation/devicetree/bindings/usb/
H A Dxlnx,usb2.yaml45 interrupts = <0x0 0x39 0x1>;
46 reg = <0xee000000 0xc00>;
/linux/drivers/staging/rtl8723bs/include/
H A DHal8192CPhyReg.h41 /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */
43 /* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */
44 /* 3. RF register 0x00-2E */
50 /* 3. Page8(0x800) */
52 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting?? */
54 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */
55 #define rFPGA0_XA_HSSIParameter2 0x824
56 #define rFPGA0_XB_HSSIParameter1 0x828
57 #define rFPGA0_XB_HSSIParameter2 0x82c
58 #define rTxAGC_B_Rate18_06 0x830
[all …]
/linux/arch/m68k/include/asm/
H A Dmac_psc.h37 #define PSC_BASE (0x50F31000)
44 * To access a particular set of registers, add 0xn0 to the base
48 #define pIFRbase 0x100
49 #define pIERbase 0x104
55 #define PSC_MYSTERY 0x804
57 #define PSC_CTL_BASE 0xC00
59 #define PSC_SCSI_CTL 0xC00
60 #define PSC_ENETRD_CTL 0xC10
61 #define PSC_ENETWR_CTL 0xC20
62 #define PSC_FDC_CTL 0xC30
[all …]
/linux/drivers/watchdog/
H A Dnpcm_wdt.c16 #define NPCM_WTCR 0x1C
25 #define NPCM_WTR BIT(0) /* Reset counter */
30 * 170 msec: WTCLK=01 WTIS=00 VAL= 0x400
31 * 670 msec: WTCLK=01 WTIS=01 VAL= 0x410
32 * 1360 msec: WTCLK=10 WTIS=00 VAL= 0x800
33 * 2700 msec: WTCLK=01 WTIS=10 VAL= 0x420
34 * 5360 msec: WTCLK=10 WTIS=01 VAL= 0x810
35 * 10700 msec: WTCLK=01 WTIS=11 VAL= 0x430
36 * 21600 msec: WTCLK=10 WTIS=10 VAL= 0x820
37 * 43000 msec: WTCLK=11 WTIS=00 VAL= 0xC00
[all …]

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