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/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_1_offset.h25 // base address: 0x8000
26 …GRBM_CNTL 0x0000
27 …ne mmGRBM_CNTL_BASE_IDX 0
28 …GRBM_SKEW_CNTL 0x0001
29 …ne mmGRBM_SKEW_CNTL_BASE_IDX 0
30 …GRBM_STATUS2 0x0002
31 …ne mmGRBM_STATUS2_BASE_IDX 0
32 …GRBM_PWR_CNTL 0x0003
33 …ne mmGRBM_PWR_CNTL_BASE_IDX 0
34 …GRBM_STATUS 0x0004
[all …]
H A Dgc_9_4_2_offset.h29 // base address: 0x0
30 …DIDT_SQ_CTRL0 0x0000
31 …DIDT_SQ_CTRL2 0x0002
32 …DIDT_SQ_STALL_CTRL 0x0004
33 …DIDT_SQ_TUNING_CTRL 0x0005
34 …DIDT_SQ_STALL_AUTO_RELEASE_CTRL 0x0006
35 …DIDT_SQ_CTRL3 0x0007
36 …DIDT_SQ_STALL_PATTERN_1_2 0x0008
37 …DIDT_SQ_STALL_PATTERN_3_4 0x0009
38 …DIDT_SQ_STALL_PATTERN_5_6 0x000a
[all …]
H A Dgc_9_1_offset.h24 …SQ_DEBUG_STS_GLOBAL 0x0309
25 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 …SQ_DEBUG_STS_GLOBAL2 0x0310
27 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
28 …SQ_DEBUG_STS_GLOBAL3 0x0311
29 …ne mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0
32 // base address: 0x8000
33 …GRBM_CNTL 0x0000
34 …ne mmGRBM_CNTL_BASE_IDX 0
35 …GRBM_SKEW_CNTL 0x0001
[all …]
H A Dgc_9_2_1_offset.h24 …SQ_DEBUG_STS_GLOBAL 0x0309
25 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 …SQ_DEBUG_STS_GLOBAL2 0x0310
27 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
28 …SQ_DEBUG_STS_GLOBAL3 0x0311
29 …ne mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0
32 // base address: 0x8000
33 …GRBM_CNTL 0x0000
34 …ne mmGRBM_CNTL_BASE_IDX 0
35 …GRBM_SKEW_CNTL 0x0001
[all …]
H A Dgc_9_4_3_offset.h29 // base address: 0x8000
30 …GRBM_CNTL 0x0000
31 …e regGRBM_CNTL_BASE_IDX 0
32 …GRBM_SKEW_CNTL 0x0001
33 …e regGRBM_SKEW_CNTL_BASE_IDX 0
34 …GRBM_STATUS2 0x0002
35 …e regGRBM_STATUS2_BASE_IDX 0
36 …GRBM_PWR_CNTL 0x0003
37 …e regGRBM_PWR_CNTL_BASE_IDX 0
38 …GRBM_STATUS 0x0004
[all …]
H A Dgc_9_0_offset.h24 …SQ_DEBUG_STS_GLOBAL 0x0309
25 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 …SQ_DEBUG_STS_GLOBAL2 0x0310
27 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
28 …SQ_DEBUG_STS_GLOBAL3 0x0311
29 …ne mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0
32 // base address: 0x8000
33 …GRBM_CNTL 0x0000
34 …ne mmGRBM_CNTL_BASE_IDX 0
35 …GRBM_SKEW_CNTL 0x0001
[all …]
/linux/arch/mips/include/asm/octeon/
H A Dcvmx-ciu-defs.h13 (CVMX_ADD_IO_SEG(0x0001070000000000ull + addr##ull) + \
16 #define CVMX_CIU_EN2_PPX_IP4(c) CVMX_CIU_ADDR(0xA400, c, 0x0F, 8)
17 #define CVMX_CIU_EN2_PPX_IP4_W1C(c) CVMX_CIU_ADDR(0xCC00, c, 0x0F, 8)
18 #define CVMX_CIU_EN2_PPX_IP4_W1S(c) CVMX_CIU_ADDR(0xAC00, c, 0x0F, 8)
19 #define CVMX_CIU_FUSE CVMX_CIU_ADDR(0x0728, 0, 0x00, 0)
20 #define CVMX_CIU_INT_SUM1 CVMX_CIU_ADDR(0x0108, 0, 0x00, 0)
21 #define CVMX_CIU_INTX_EN0(c) CVMX_CIU_ADDR(0x0200, c, 0x3F, 16)
22 #define CVMX_CIU_INTX_EN0_W1C(c) CVMX_CIU_ADDR(0x2200, c, 0x3F, 16)
23 #define CVMX_CIU_INTX_EN0_W1S(c) CVMX_CIU_ADDR(0x6200, c, 0x3F, 16)
24 #define CVMX_CIU_INTX_EN1(c) CVMX_CIU_ADDR(0x0208, c, 0x3F, 16)
[all …]
/linux/drivers/staging/media/meson/vdec/
H A Dcodec_hevc_common.c13 #define MMU_COMPRESS_HEADER_SIZE 0x48000
14 #define MMU_MAP_SIZE 0x4800
17 0x0401, 0x8401, 0x0800, 0x0402,
18 0x9002, 0x1423, 0x8CC3, 0x1423,
19 0x8804, 0x9825, 0x0800, 0x04FE,
20 0x8406, 0x8411, 0x1800, 0x8408,
21 0x8409, 0x8C2A, 0x9C2B, 0x1C00,
22 0x840F, 0x8407, 0x8000, 0x8408,
23 0x2000, 0xA800, 0x8410, 0x04DE,
24 0x840C, 0x840D, 0xAC00, 0xA000,
[all …]
/linux/drivers/clk/imx/
H A Dclk-imx7d.c32 { .val = 0, .div = 4, },
40 { .val = 0, .div = 1, },
393 hws[IMX7D_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx7d_clocks_init()
398 base = of_iomap(np, 0); in imx7d_clocks_init()
402 …hws[IMX7D_PLL_ARM_MAIN_SRC] = imx_clk_hw_mux("pll_arm_main_src", base + 0x60, 14, 2, pll_bypass_s… in imx7d_clocks_init()
403 …hws[IMX7D_PLL_DRAM_MAIN_SRC] = imx_clk_hw_mux("pll_dram_main_src", base + 0x70, 14, 2, pll_bypass_… in imx7d_clocks_init()
404 …hws[IMX7D_PLL_SYS_MAIN_SRC] = imx_clk_hw_mux("pll_sys_main_src", base + 0xb0, 14, 2, pll_bypass_s… in imx7d_clocks_init()
405 …hws[IMX7D_PLL_ENET_MAIN_SRC] = imx_clk_hw_mux("pll_enet_main_src", base + 0xe0, 14, 2, pll_bypass_… in imx7d_clocks_init()
406 …hws[IMX7D_PLL_AUDIO_MAIN_SRC] = imx_clk_hw_mux("pll_audio_main_src", base + 0xf0, 14, 2, pll_bypas… in imx7d_clocks_init()
407 …hws[IMX7D_PLL_VIDEO_MAIN_SRC] = imx_clk_hw_mux("pll_video_main_src", base + 0x130, 14, 2, pll_bypa… in imx7d_clocks_init()
[all …]
H A Dclk-imx8mn.c334 hws[IMX8MN_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mn_clocks_probe()
343 base = devm_of_iomap(dev, np, 0, NULL); in imx8mn_clocks_probe()
350 …hws[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_se… in imx8mn_clocks_probe()
351 …hws[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_s… in imx8mn_clocks_probe()
352 …hws[IMX8MN_VIDEO_PLL_REF_SEL] = imx_clk_hw_mux("video_pll_ref_sel", base + 0x28, 0, 2, pll_ref_sel… in imx8mn_clocks_probe()
353 …hws[IMX8MN_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels,… in imx8mn_clocks_probe()
354 …hws[IMX8MN_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, A… in imx8mn_clocks_probe()
355 …hws[IMX8MN_M7_ALT_PLL_REF_SEL] = imx_clk_hw_mux("m7_alt_pll_ref_sel", base + 0x74, 0, 2, pll_ref_s… in imx8mn_clocks_probe()
356 …hws[IMX8MN_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, A… in imx8mn_clocks_probe()
357 …hws[IMX8MN_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels… in imx8mn_clocks_probe()
[all …]
H A Dclk-imx8mm.c314 hws[IMX8MM_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mm_clocks_probe()
323 base = of_iomap(np, 0); in imx8mm_clocks_probe()
328 …hws[IMX8MM_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_se… in imx8mm_clocks_probe()
329 …hws[IMX8MM_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_s… in imx8mm_clocks_probe()
330 …hws[IMX8MM_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_s… in imx8mm_clocks_probe()
331 …hws[IMX8MM_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels,… in imx8mm_clocks_probe()
332 …hws[IMX8MM_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, A… in imx8mm_clocks_probe()
333 …hws[IMX8MM_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, A… in imx8mm_clocks_probe()
334 …hws[IMX8MM_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, A… in imx8mm_clocks_probe()
335 …hws[IMX8MM_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels… in imx8mm_clocks_probe()
[all …]
H A Dclk-imx8mq.c298 hws[IMX8MQ_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mq_clocks_probe()
308 base = devm_of_iomap(dev, np, 0, NULL); in imx8mq_clocks_probe()
315 …hws[IMX8MQ_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x28, 16, 2, pll_ref_sels, … in imx8mq_clocks_probe()
316 …hws[IMX8MQ_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x18, 16, 2, pll_ref_sels, … in imx8mq_clocks_probe()
317 …hws[IMX8MQ_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x20, 16, 2, pll_ref_sels, … in imx8mq_clocks_probe()
318 …hws[IMX8MQ_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 16, 2, pll_ref_s… in imx8mq_clocks_probe()
319 …hws[IMX8MQ_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x8, 16, 2, pll_ref_s… in imx8mq_clocks_probe()
320 …hws[IMX8MQ_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x10, 16, 2, pll_ref_… in imx8mq_clocks_probe()
321 …hws[IMX8MQ_SYS3_PLL1_REF_SEL] = imx_clk_hw_mux("sys3_pll1_ref_sel", base + 0x48, 0, 2, pll_ref_sel… in imx8mq_clocks_probe()
322 …hws[IMX8MQ_DRAM_PLL1_REF_SEL] = imx_clk_hw_mux("dram_pll1_ref_sel", base + 0x60, 0, 2, pll_ref_sel… in imx8mq_clocks_probe()
[all …]
/linux/fs/unicode/
H A Dmkutf8data.c50 int verbose = 0;
63 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
98 return 0; in age_valid()
100 return 0; in age_valid()
102 return 0; in age_valid()
119 * if offlen == 0 (non-branching node)
124 * if offlen != 0 (branching node)
133 #define BITNUM 0x07
134 #define NEXTBYTE 0x08
135 #define OFFLEN 0x30
[all …]
/linux/fs/hfsplus/
H A Dunicode.c18 /* Returns folded char, or 0 if ignorable */
25 tmp = hfsplus_case_fold_table[tmp + (c & 0xff)]; in case_fold()
44 c1 = c2 = 0; in hfsplus_strcasecmp()
60 return 0; in hfsplus_strcasecmp()
77 for (len = min(len1, len2); len > 0; len--) { in hfsplus_strcmp()
87 len1 > len2 ? 1 : 0; in hfsplus_strcmp()
91 #define Hangul_SBase 0xac00
92 #define Hangul_LBase 0x1100
93 #define Hangul_VBase 0x1161
94 #define Hangul_TBase 0x11a7
[all …]
/linux/drivers/net/wireless/mediatek/mt7601u/
H A Dregs.h12 #define MT_ASIC_VERSION 0x0000
14 #define MT76XX_REV_E3 0x22
15 #define MT76XX_REV_E4 0x33
17 #define MT_CMB_CTRL 0x0020
21 #define MT_EFUSE_CTRL 0x0024
22 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
30 #define MT_EFUSE_DATA_BASE 0x0028
33 #define MT_COEXCFG0 0x0040
34 #define MT_COEXCFG0_COEX_EN BIT(0)
36 #define MT_WLAN_FUN_CTRL 0x0080
[all …]
/linux/drivers/net/wireless/mediatek/mt76/
H A Dmt76x02_regs.h9 #define MT_ASIC_VERSION 0x0000
11 #define MT76XX_REV_E3 0x22
12 #define MT76XX_REV_E4 0x33
14 #define MT_CMB_CTRL 0x0020
18 #define MT_EFUSE_CTRL 0x0024
19 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
27 #define MT_EFUSE_DATA_BASE 0x0028
30 #define MT_COEXCFG0 0x0040
31 #define MT_COEXCFG0_COEX_EN BIT(0)
33 #define MT_WLAN_FUN_CTRL 0x0080
[all …]
/linux/drivers/gpu/drm/msm/adreno/
H A Da6xx_gpu_state.h16 0x8000, 0x8006, 0x8010, 0x8092, 0x8094, 0x809d, 0x80a0, 0x80a6,
17 0x80af, 0x80f1, 0x8100, 0x8107, 0x8109, 0x8109, 0x8110, 0x8110,
18 0x8400, 0x840b,
22 0x8800, 0x8806, 0x8809, 0x8811, 0x8818, 0x881e, 0x8820, 0x8865,
23 0x8870, 0x8879, 0x8880, 0x8889, 0x8890, 0x8891, 0x8898, 0x8898,
24 0x88c0, 0x88c1, 0x88d0, 0x88e3, 0x8900, 0x890c, 0x890f, 0x891a,
25 0x8c00, 0x8c01, 0x8c08, 0x8c10, 0x8c17, 0x8c1f, 0x8c26, 0x8c33,
29 0x88f0, 0x88f3, 0x890d, 0x890e, 0x8927, 0x8928, 0x8bf0, 0x8bf1,
30 0x8c02, 0x8c07, 0x8c11, 0x8c16, 0x8c20, 0x8c25,
34 0x9200, 0x9216, 0x9218, 0x9236, 0x9300, 0x9306,
[all …]
/linux/drivers/input/misc/
H A Diqs7222.c25 #define IQS7222_PROD_NUM 0x00
31 #define IQS7222_SYS_STATUS 0x10
34 #define IQS7222_SYS_STATUS_ATI_ACTIVE BIT(0)
41 #define IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK GENMASK(2, 0)
44 #define IQS7222_SLDR_SETUP_2_TOP_SPEED_MASK GENMASK(7, 0)
46 #define IQS7222_GPIO_SETUP_0_GPIO_EN BIT(0)
48 #define IQS7222_SYS_SETUP 0xD0
55 #define IQS7222_SYS_SETUP_ACK_RESET BIT(0)
61 #define IQS7222_EVENT_MASK_PROX BIT(0)
63 #define IQS7222_COMMS_HOLD BIT(0)
[all …]
/linux/drivers/tty/vt/
H A Ducs_width_table.h_shipped7 * Unicode Version: 16.0.0
12 { 0x00AD, 0x00AD }, /* SOFT HYPHEN */
13 { 0x0300, 0x036F }, /* COMBINING GRAVE ACCENT - COMBINING LATIN SMALL LETTER X */
14 { 0x0483, 0x0489 }, /* COMBINING CYRILLIC TITLO - COMBINING CYRILLIC MILLIONS SIGN */
15 { 0x0591, 0x05BD }, /* HEBREW ACCENT ETNAHTA - HEBREW POINT METEG */
16 { 0x05BF, 0x05BF }, /* HEBREW POINT RAFE */
17 { 0x05C1, 0x05C2 }, /* HEBREW POINT SHIN DOT - HEBREW POINT SIN DOT */
18 { 0x05C4, 0x05C5 }, /* HEBREW MARK UPPER DOT - HEBREW MARK LOWER DOT */
19 { 0x05C7, 0x05C7 }, /* HEBREW POINT QAMATS QATAN */
20 { 0x0600, 0x0605 }, /* ARABIC NUMBER SIGN - ARABIC NUMBER MARK ABOVE */
[all …]
/linux/include/video/
H A Dpm3fb.h19 #define PM3ResetStatus 0x0000
20 #define PM3IntEnable 0x0008
21 #define PM3IntFlags 0x0010
22 #define PM3InFIFOSpace 0x0018
23 #define PM3OutFIFOWords 0x0020
24 #define PM3DMAAddress 0x0028
25 #define PM3DMACount 0x0030
26 #define PM3ErrorFlags 0x0038
27 #define PM3VClkCtl 0x0040
28 #define PM3TestRegister 0x0048
[all …]
/linux/drivers/net/phy/
H A Dnxp-c45-tja11xx.c23 #define PHY_ID_TJA_1103 0x001BB010
25 #define PHY_ID_TJA_1120 0x001BB031
27 #define VEND1_DEVICE_ID3 0x0004
30 #define DEVICE_ID3_SAMPLE_TYPE_R 0x9
32 #define VEND1_DEVICE_CONTROL 0x0040
37 #define VEND1_DEVICE_CONFIG 0x0048
39 #define TJA1120_VEND1_EXT_TS_MODE 0x1012
41 #define TJA1120_GLOBAL_INFRA_IRQ_ACK 0x2C08
42 #define TJA1120_GLOBAL_INFRA_IRQ_EN 0x2C0A
43 #define TJA1120_GLOBAL_INFRA_IRQ_STATUS 0x2C0C
[all …]
/linux/sound/soc/codecs/
H A Drt5682.c43 {RT5682_HP_IMP_SENS_CTRL_19, 0x1000},
44 {RT5682_DAC_ADC_DIG_VOL1, 0xa020},
45 {RT5682_I2C_CTRL, 0x000f},
46 {RT5682_PLL2_INTERNAL, 0x8266},
47 {RT5682_SAR_IL_CMD_1, 0x22b7},
48 {RT5682_SAR_IL_CMD_3, 0x0365},
49 {RT5682_SAR_IL_CMD_6, 0x0110},
50 {RT5682_CHARGE_PUMP_1, 0x0210},
51 {RT5682_HP_LOGIC_CTRL_2, 0x0007},
52 {RT5682_SAR_IL_CMD_2, 0xac00},
[all …]
H A Drt5682s.c32 #define DEVICE_ID 0x6749
50 {RT5682S_I2C_CTRL, 0x0007},
51 {RT5682S_DIG_IN_CTRL_1, 0x0000},
52 {RT5682S_CHOP_DAC_2, 0x2020},
53 {RT5682S_VREF_REC_OP_FB_CAP_CTRL_2, 0x0101},
54 {RT5682S_VREF_REC_OP_FB_CAP_CTRL_1, 0x80c0},
55 {RT5682S_HP_CALIB_CTRL_9, 0x0002},
56 {RT5682S_DEPOP_1, 0x0000},
57 {RT5682S_HP_CHARGE_PUMP_2, 0x3c15},
58 {RT5682S_DAC1_DIG_VOL, 0xfefe},
[all …]
/linux/drivers/hid/
H A Dhid-nintendo.c51 #define JC_OUTPUT_RUMBLE_AND_SUBCMD 0x01
52 #define JC_OUTPUT_FW_UPDATE_PKT 0x03
53 #define JC_OUTPUT_RUMBLE_ONLY 0x10
54 #define JC_OUTPUT_MCU_DATA 0x11
55 #define JC_OUTPUT_USB_CMD 0x80
58 #define JC_SUBCMD_STATE 0x00
59 #define JC_SUBCMD_MANUAL_BT_PAIRING 0x01
60 #define JC_SUBCMD_REQ_DEV_INFO 0x02
61 #define JC_SUBCMD_SET_REPORT_MODE 0x03
62 #define JC_SUBCMD_TRIGGERS_ELAPSED 0x04
[all …]
/linux/drivers/gpu/drm/msm/registers/adreno/
H A Da5xx.xml10 <value value="0x02" name="RB5_A8_UNORM"/>
11 <value value="0x03" name="RB5_R8_UNORM"/>
12 <value value="0x04" name="RB5_R8_SNORM"/>
13 <value value="0x05" name="RB5_R8_UINT"/>
14 <value value="0x06" name="RB5_R8_SINT"/>
15 <value value="0x08" name="RB5_R4G4B4A4_UNORM"/>
16 <value value="0x0a" name="RB5_R5G5B5A1_UNORM"/>
17 <value value="0x0e" name="RB5_R5G6B5_UNORM"/>
18 <value value="0x0f" name="RB5_R8G8_UNORM"/>
19 <value value="0x10" name="RB5_R8G8_SNORM"/>
[all …]

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