Searched +full:0 +full:xa0080000 (Results 1 – 4 of 4) sorted by relevance
25 /* The maximum IRQ pin number of mbigen chip(start from 0) */31 * bit[11:0]: device id34 #define IRQ_EVENT_ID_MASK 0x3ff37 #define MBIGEN_NODE_OFFSET 0x100040 #define REG_MBIGEN_VEC_OFFSET 0x20047 #define REG_MBIGEN_CLEAR_OFFSET 0xa00054 #define REG_MBIGEN_TYPE_OFFSET 0x0147 return 0; in mbigen_set_type()177 if ((fwspec->param[0] > MAXIMUM_IRQ_PIN_NUM) || in mbigen_domain_translate()178 (fwspec->param[0] < RESERVED_IRQ_PER_MBIGEN_CHIP)) in mbigen_domain_translate()[all …]
35 * it to resume execution at 0x8000_0200 (!BEV IV vector) when it is37 * it to a more convenient place: BMIPS_WARM_RESTART_VEC @ 0x8000_0380.54 /* set up CPU1 CBR; move BASE to 0xa000_0000 */55 li k0, 0xff40000060 andi k1, 0x800063 li k1, 0xa008000064 sw k1, 0(k0)78 * entire function gets copied to 0x8000_0000.100 /* if we're not on core 0, this must be the SMP boot signal */134 andi k0, 0xff00[all …]
23 #size-cells = <0>;87 reg = <0x10000>;95 reg = <0x10001>;103 reg = <0x10002>;111 reg = <0x10003>;119 reg = <0x10100>;127 reg = <0x10101>;135 reg = <0x10102>;143 reg = <0x10103>;151 reg = <0x10200>;[all …]
23 #size-cells = <0>;270 reg = <0x10000>;273 numa-node-id = <0>;279 reg = <0x10001>;282 numa-node-id = <0>;288 reg = <0x10002>;291 numa-node-id = <0>;297 reg = <0x10003>;300 numa-node-id = <0>;306 reg = <0x10100>;[all …]