Lines Matching +full:0 +full:xa0080000
25 /* The maximum IRQ pin number of mbigen chip(start from 0) */
31 * bit[11:0]: device id
34 #define IRQ_EVENT_ID_MASK 0x3ff
37 #define MBIGEN_NODE_OFFSET 0x1000
40 #define REG_MBIGEN_VEC_OFFSET 0x200
47 #define REG_MBIGEN_CLEAR_OFFSET 0xa000
54 #define REG_MBIGEN_TYPE_OFFSET 0x0
147 return 0; in mbigen_set_type()
177 if ((fwspec->param[0] > MAXIMUM_IRQ_PIN_NUM) || in mbigen_domain_translate()
178 (fwspec->param[0] < RESERVED_IRQ_PER_MBIGEN_CHIP)) in mbigen_domain_translate()
181 *hwirq = fwspec->param[0]; in mbigen_domain_translate()
190 return 0; in mbigen_domain_translate()
248 &num_pins) < 0) { in mbigen_of_create_domain()
257 return 0; in mbigen_of_create_domain()
262 { "HISI0152", 0 },
270 u32 num_pins = 0; in mbigen_acpi_create_domain()
285 * Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) in mbigen_acpi_create_domain()
297 if (ret || num_pins == 0) in mbigen_acpi_create_domain()
303 return 0; in mbigen_acpi_create_domain()
325 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); in mbigen_device_probe()
349 return 0; in mbigen_device_probe()