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/linux/arch/arm64/boot/dts/marvell/mmp/
H A Dpxa1908-samsung-coreprimevelte.dts25 reg = <0 0x17177000 0 (480 * 800 * 4)>;
34 memory@0 {
36 reg = <0 0 0 0>;
45 reg = <0 0x17000000 0 0x1800000>;
50 reg = <0 0x9000000 0 0x1000000>;
55 reg = <0 0x5000000 0 0x3000000>;
59 reg = <0 0xa000000 0 0x80000>;
63 reg = <0 0x8000000 0 0x100000>;
68 reg = <0 0x8100000 0 0x40000>;
69 record-size = <0x8000>;
[all …]
/linux/arch/powerpc/boot/dts/
H A Dmvme5100.dts26 #size-cells = <0>;
30 reg = <0x0>;
44 reg = <0x0 0x20000000>;
51 ranges = <0x0 0xfef80000 0x10000>;
52 reg = <0xfef80000 0x10000>;
57 reg = <0x8000 0x80>;
68 reg = <0x8200 0x80>;
78 #address-cells = <0>;
82 reg = <0xf3f80000 0x40000>;
92 reg = <0xfec00000 0x400000>;
[all …]
H A Dstxssa8555.dts30 #size-cells = <0>;
32 PowerPC,8555@0 {
34 reg = <0x0>;
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
39 timebase-frequency = <0>; // 33 MHz, from uboot
40 bus-frequency = <0>; // 166 MHz
41 clock-frequency = <0>; // 825 MHz, from uboot
48 reg = <0x00000000 0x10000000>;
56 ranges = <0x0 0xe0000000 0x100000>;
[all …]
/linux/sound/soc/codecs/
H A Drt274.h14 #define RT274_AUDIO_FUNCTION_GROUP 0x01
15 #define RT274_DAC_OUT0 0x02
16 #define RT274_DAC_OUT1 0x03
17 #define RT274_ADC_IN2 0x08
18 #define RT274_ADC_IN1 0x09
19 #define RT274_DIG_CVT 0x0a
20 #define RT274_DMIC1 0x12
21 #define RT274_DMIC2 0x13
22 #define RT274_MIC 0x19
23 #define RT274_LINE1 0x1a
[all …]
H A Drt286.h14 #define RT286_AUDIO_FUNCTION_GROUP 0x01
15 #define RT286_DAC_OUT1 0x02
16 #define RT286_DAC_OUT2 0x03
17 #define RT286_ADC_IN1 0x09
18 #define RT286_ADC_IN2 0x08
19 #define RT286_MIXER_IN 0x0b
20 #define RT286_MIXER_OUT1 0x0c
21 #define RT286_MIXER_OUT2 0x0d
22 #define RT286_DMIC1 0x12
23 #define RT286_DMIC2 0x13
[all …]
H A Drt298.h14 #define RT298_AUDIO_FUNCTION_GROUP 0x01
15 #define RT298_DAC_OUT1 0x02
16 #define RT298_DAC_OUT2 0x03
17 #define RT298_DIG_CVT 0x06
18 #define RT298_ADC_IN1 0x09
19 #define RT298_ADC_IN2 0x08
20 #define RT298_MIXER_IN 0x0b
21 #define RT298_MIXER_OUT1 0x0c
22 #define RT298_MIXER_OUT2 0x0d
23 #define RT298_DMIC1 0x12
[all …]
/linux/drivers/net/usb/
H A Dr8153_ecm.c10 #define OCP_BASE 0xe86c
26 if (ret < 0) in pla_read_word()
31 ret &= 0xffff; in pla_read_word()
39 u32 mask = 0xffff; in pla_write_word()
58 if (ret < 0) in pla_write_word()
76 ret = pla_write_word(dev, OCP_BASE, 0xa000); in r8153_ecm_mdio_read()
77 if (ret < 0) in r8153_ecm_mdio_read()
80 ret = pla_read_word(dev, 0xb400 + reg * 2); in r8153_ecm_mdio_read()
91 ret = pla_write_word(dev, OCP_BASE, 0xa000); in r8153_ecm_mdio_write()
92 if (ret < 0) in r8153_ecm_mdio_write()
[all …]
/linux/arch/mips/sgi-ip22/
H A Dip22-nvram.c13 #define EEPROM_READ 0xc000 /* serial memory read */
14 #define EEPROM_WEN 0x9800 /* write enable before prog modes */
15 #define EEPROM_WRITE 0xa000 /* serial memory write */
16 #define EEPROM_WRALL 0x8800 /* write all registers */
17 #define EEPROM_WDS 0x8000 /* disable all programming */
18 #define EEPROM_PRREAD 0xc000 /* read protect register */
19 #define EEPROM_PREN 0x9800 /* enable protect register mode */
20 #define EEPROM_PRCLEAR 0xffff /* clear protect register */
21 #define EEPROM_PRWRITE 0xa000 /* write protect register */
22 #define EEPROM_PRDS 0x8000 /* disable protect register, forever */
[all …]
/linux/Documentation/devicetree/bindings/mailbox/
H A Dxgene-slimpro-mailbox.txt14 - interrupts: 8 interrupts must be from 0 to 7, interrupt 0 define the
15 the interrupt for mailbox channel 0 and interrupt 1 for
25 reg = <0x0 0x10540000 0x0 0xa000>;
27 interrupts = <0x0 0x0 0x4>,
28 <0x0 0x1 0x4>,
29 <0x0 0x2 0x4>,
30 <0x0 0x3 0x4>,
31 <0x0 0x4 0x4>,
32 <0x0 0x5 0x4>,
33 <0x0 0x6 0x4>,
[all …]
/linux/arch/arm/boot/dts/qcom/
H A Dpm8841.dtsi10 polling-delay = <0>;
40 reg = <0x4 SPMI_USID>;
42 #size-cells = <0>;
46 reg = <0xa000>;
49 gpio-ranges = <&pm8841_mpps 0 0 4>;
56 reg = <0x2400>;
57 interrupts = <4 0x24 0 IRQ_TYPE_EDGE_RISING>;
58 #thermal-sensor-cells = <0>;
64 reg = <0x5 SPMI_USID>;
66 #size-cells = <0>;
H A Dpma8084.dtsi9 pma8084_0: pma8084@0 {
11 reg = <0x0 SPMI_USID>;
13 #size-cells = <0>;
17 reg = <0x6000>,
18 <0x6100>;
20 interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
25 reg = <0x800>;
29 interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
38 reg = <0xc000>;
40 gpio-ranges = <&pma8084_gpios 0 0 22>;
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dpmi8994.dtsi9 reg = <0x2 SPMI_USID>;
11 #size-cells = <0>;
15 reg = <0xc000>;
17 gpio-ranges = <&pmi8994_gpios 0 0 10>;
25 reg = <0xa000>;
27 gpio-ranges = <&pmi8994_mpps 0 0 4>;
36 reg = <0x3 SPMI_USID>;
38 #size-cells = <0>;
44 #size-cells = <0>;
56 reg = <0xd800>, <0xd900>;
[all …]
H A Dpm8937.dtsi13 polling-delay-passive = <0>;
14 polling-delay = <0>;
20 hysteresis = <0>;
26 hysteresis = <0>;
32 hysteresis = <0>;
41 pmic@0 {
43 reg = <0x0 SPMI_USID>;
45 #size-cells = <0>;
49 reg = <0x800>;
50 mode-bootloader = <0x2>;
[all …]
/linux/Documentation/i2c/
H A Dten-bit-addresses.rst7 do not intersect: the 7 bit address 0x10 is not the same as the 10 bit
8 address 0x10 (though a single device could respond to both of them).
10 address space, namely 0xa000-0xa3ff. The leading 0xa (= 10) represents the
/linux/arch/arm64/include/asm/
H A Ddebug-monitors.h18 #define DBG_ESR_EVT(x) (((x) >> 27) & 0x7)
21 #define DBG_ESR_EVT_HWBP 0x0
22 #define DBG_ESR_EVT_HWSS 0x1
23 #define DBG_ESR_EVT_HWWP 0x2
24 #define DBG_ESR_EVT_BRK 0x6
43 #define DBG_ESR_EVT_BKPT 0x4
44 #define DBG_ESR_EVT_VECC 0x5
46 #define AARCH32_BREAK_ARM 0x07f001f0
47 #define AARCH32_BREAK_THUMB 0xde01
48 #define AARCH32_BREAK_THUMB2_LO 0xf7f0
[all …]
/linux/arch/loongarch/include/asm/
H A Dkasan.h21 #define XRANGE_SHADOW_MASK GENMASK_ULL(XRANGE_SHADOW_SHIFT - 1, 0)
26 #define XKPRANGE_UC_SEG (0x8000)
27 #define XKPRANGE_CC_SEG (0x9000)
28 #define XKPRANGE_WC_SEG (0xa000)
29 #define XKVRANGE_VC_SEG (0xffff)
34 #define XKPRANGE_CC_KASAN_OFFSET (0)
/linux/drivers/usb/storage/
H A Dunusual_datafab.h9 UNUSUAL_DEV( 0x07c4, 0xa000, 0x0000, 0x0015,
13 0),
17 * using the current driver...the 0xffff is arbitrary since I
20 * The 0xa003 and 0xa004 devices in particular I'm curious about.
26 UNUSUAL_DEV( 0x07c4, 0xa001, 0x0000, 0xffff,
30 0),
33 UNUSUAL_DEV( 0x07c4, 0xa002, 0x0000, 0xffff,
39 UNUSUAL_DEV( 0x07c4, 0xa003, 0x0000, 0xffff,
43 0),
45 UNUSUAL_DEV( 0x07c4, 0xa004, 0x0000, 0xffff,
[all …]
/linux/drivers/net/ethernet/apm/xgene-v2/
H A Dmac.h14 #define MAC_CONFIG_1 0xa000
15 #define MAC_CONFIG_2 0xa004
16 #define MII_MGMT_CONFIG 0xa020
17 #define MII_MGMT_COMMAND 0xa024
18 #define MII_MGMT_ADDRESS 0xa028
19 #define MII_MGMT_CONTROL 0xa02c
20 #define MII_MGMT_STATUS 0xa030
21 #define MII_MGMT_INDICATORS 0xa034
22 #define INTERFACE_CONTROL 0xa038
23 #define STATION_ADDR0 0xa040
[all …]
/linux/drivers/accel/habanalabs/include/gaudi/asic_reg/
H A Dgaudi_blocks.h16 #define mmNIC0_PHY0_BASE 0x0ull
17 #define NIC0_PHY0_MAX_OFFSET 0x9F13
18 #define mmMME0_ACC_BASE 0x7FFC020000ull
19 #define MME0_ACC_MAX_OFFSET 0x5C00
20 #define MME0_ACC_SECTION 0x20000
21 #define mmMME0_SBAB_BASE 0x7FFC040000ull
22 #define MME0_SBAB_MAX_OFFSET 0x5800
23 #define MME0_SBAB_SECTION 0x1000
24 #define mmMME0_PRTN_BASE 0x7FFC041000ull
25 #define MME0_PRTN_MAX_OFFSET 0x5000
[all …]
/linux/arch/arm/boot/dts/arm/
H A Dversatile-pb.dts11 clear-mask = <0xffffffff>;
16 valid-mask = <0x7fe003ff>;
21 reg = <0x101e6000 0x1000>;
33 reg = <0x101e7000 0x1000>;
46 reg = <0x10001000 0x1000
47 0x41000000 0x10000
48 0x42000000 0x100000>;
49 bus-range = <0 0xff>;
54 ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000 /* downstream I/O */
55 0x02000000 0 0x50000000 0x50000000 0 0x10000000 /* non-prefetchable memory */
[all …]
/linux/drivers/media/platform/mediatek/vcodec/decoder/
H A Dvdec_ipi_msg.h16 AP_IPIMSG_DEC_INIT = 0xA000,
17 AP_IPIMSG_DEC_START = 0xA001,
18 AP_IPIMSG_DEC_END = 0xA002,
19 AP_IPIMSG_DEC_DEINIT = 0xA003,
20 AP_IPIMSG_DEC_RESET = 0xA004,
21 AP_IPIMSG_DEC_CORE = 0xA005,
22 AP_IPIMSG_DEC_CORE_END = 0xA006,
23 AP_IPIMSG_DEC_GET_PARAM = 0xA007,
25 VPU_IPIMSG_DEC_INIT_ACK = 0xB000,
26 VPU_IPIMSG_DEC_START_ACK = 0xB001,
[all …]
/linux/drivers/media/usb/dvb-usb/
H A Daf9005-script.h19 {0xa180, 0x0, 0x8, 0xa},
20 {0xa181, 0x0, 0x8, 0xd7},
21 {0xa182, 0x0, 0x8, 0xa3},
22 {0xa0a0, 0x0, 0x8, 0x0},
23 {0xa0a1, 0x0, 0x5, 0x0},
24 {0xa0a1, 0x5, 0x1, 0x1},
25 {0xa0c0, 0x0, 0x4, 0x1},
26 {0xa20e, 0x4, 0x4, 0xa},
27 {0xa20f, 0x0, 0x8, 0x40},
28 {0xa210, 0x0, 0x8, 0x8},
[all …]
/linux/arch/mips/boot/dts/brcm/
H A Dbcm7360.dtsi9 #size-cells = <0>;
13 cpu@0 {
16 reg = <0>;
25 #address-cells = <0>;
35 #clock-cells = <0>;
41 #clock-cells = <0>;
51 ranges = <0 0x10000000 0x01000000>;
55 reg = <0x411400 0x30>;
66 reg = <0x403000 0x30>;
75 reg = <0x400000 0xdc>;
[all …]
H A Dbcm7362.dtsi9 #size-cells = <0>;
13 cpu@0 {
16 reg = <0>;
31 #address-cells = <0>;
41 #clock-cells = <0>;
47 #clock-cells = <0>;
57 ranges = <0 0x10000000 0x01000000>;
61 reg = <0x411400 0x30>, <0x411600 0x30>;
72 reg = <0x403000 0x30>;
81 reg = <0x400000 0xdc>;
[all …]
/linux/arch/arm/mach-mv78xx0/
H A Dmv78xx0.h17 * f0800000 PCIe #0 I/O space
29 * fee00000 f0800000 64K PCIe #0 I/O space
39 #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
40 #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
41 #define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000)
42 #define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000
45 #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
48 #define MV78XX0_REGS_PHYS_BASE 0xf1000000
49 #define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000)
52 #define MV78XX0_SRAM_PHYS_BASE (0xf2200000)
[all …]

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