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/freebsd/sys/contrib/device-tree/Bindings/display/mediatek/
H A Dmediatek,hdmi.txt19 configuration registers. For mt8173 this must be offset 0x900 into the
20 MMSYS_CONFIG region: <&mmsys 0x900>.
23 - port@0: The input port in the ports node should be connected to a DPI output
62 reg = <0 0x10013000 0 0xbc>;
69 reg = <0 0x10209100 0 0x24>;
73 mediatek,ibias = <0xa>;
74 mediatek,ibias_up = <0x1c>;
75 #clock-cells = <0>;
76 #phy-cells = <0>;
81 reg = <0 0x11012000 0 0x1c>;
[all …]
H A Dmediatek,hdmi.yaml65 port@0:
78 - port@0
101 reg = <0x14025000 0x400>;
109 pinctrl-0 = <&hdmi_pin>;
112 mediatek,syscon-hdmi = <&mmsys 0x900>;
116 #size-cells = <0>;
118 port@0 {
119 reg = <0>;
/freebsd/sys/contrib/device-tree/Bindings/display/bridge/
H A Dptn3460.txt11 | 0 | 1024x768 | NXP Generic |
14 | 3 | 1600x900 | Samsung LTM200KT |
17 | 6 | 1600x900 | ChiMei M215HGE |
28 reg = <0x20>;
29 powerdown-gpio = <&gpy2 5 1 0 0>;
30 reset-gpio = <&gpx1 5 1 0 0>;
33 port@0 {
H A Dnxp,ptn3460.yaml25 0 1024x768 NXP Generic
28 3 1600x900 Samsung LTM200KT
31 6 1600x900 ChiMei M215HGE
32 enum: [0, 1, 2, 3, 4, 5, 6]
46 port@0:
57 - port@0
76 #size-cells = <0>;
80 reg = <0x20>;
87 #size-cells = <0>;
89 port@0 {
[all …]
/freebsd/sys/dev/drm2/
H A Ddrm_edid_modes.h36 736, 832, 0, 350, 382, 385, 445, 0,
40 736, 832, 0, 400, 401, 404, 445, 0,
44 828, 936, 0, 400, 401, 404, 446, 0,
48 752, 800, 0, 480, 489, 492, 525, 0,
52 704, 832, 0, 480, 489, 492, 520, 0,
56 720, 840, 0, 480, 481, 484, 500, 0,
60 752, 832, 0, 480, 481, 484, 509, 0,
64 896, 1024, 0, 600, 601, 603, 625, 0,
68 968, 1056, 0, 600, 601, 605, 628, 0,
72 976, 1040, 0, 600, 637, 643, 666, 0,
[all …]
/freebsd/contrib/llvm-project/compiler-rt/lib/hwasan/
H A Dhwasan_checks.h3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
29 return 0x20 * (EA == ErrorAction::Recover) + in SigTrapEncoding()
30 0x10 * (AT == AccessType::Store) + LogSize; in SigTrapEncoding()
35 return SigTrapEncoding(EA, AT, 0xf); in SigTrapEncoding()
53 HandleTagMismatch(access_info, (uptr)__builtin_return_address(0), in SigTrap()
54 (uptr)__builtin_frame_address(0), /*uc=*/nullptr, regs.x); in SigTrap()
57 // 0x900 is added to do not interfere with the kernel use of lower values of in SigTrap()
60 asm("brk %1\n\t" ::"r"(x0), "n"(0x900 + SigTrapEncoding(EA, AT, LogSize))); in SigTrap()
64 // 0x40 is added as a safeguard, to help distinguish our trap from others and in SigTrap()
65 // to avoid 0 offsets in the command (otherwise it'll be reduced to a in SigTrap()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/i2c/
H A Di2c-mt7621.txt8 - #size-cells: should be 0.
20 reg = <0x900 0x100>;
22 #size-cells = <0>;
H A Dmediatek,mt7621-i2c.yaml50 reg = <0x900 0x100>;
57 #size-cells = <0>;
60 pinctrl-0 = <&i2c_pins>;
/freebsd/sys/contrib/device-tree/Bindings/crypto/
H A Dbrcm,spu-crypto.txt20 reg = <0 0x612d0000 0 0x900>;
21 mboxes = <&pdc0 0>;
/freebsd/sys/contrib/device-tree/Bindings/extcon/
H A Dqcom,pm8941-misc.txt33 reg = <0x900>;
34 interrupts = <0x0 0x9 0 IRQ_TYPE_EDGE_BOTH>;
H A Dqcom,pm8941-misc.yaml52 #size-cells = <0>;
58 reg = <0x900>;
59 interrupts = <0x0 0x9 0 IRQ_TYPE_EDGE_BOTH>;
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dfsl,flexspi-clock.yaml29 const: 0
50 reg = <0x900 0x4>;
51 #clock-cells = <0>;
/freebsd/sys/contrib/device-tree/src/arm64/broadcom/northstar2/
H A Dns2.dtsi33 /memreserve/ 0x81000000 0x00200000;
46 #size-cells = <0>;
48 A57_0: cpu@0 {
51 reg = <0 0>;
59 reg = <0 1>;
67 reg = <0 2>;
75 reg = <0 3>;
80 CLUSTER0_L2: l2-cache@0 {
94 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
96 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |
[all …]
/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dlpc18xx-ccu.h13 #define CLK_APB3_BUS 0x100
14 #define CLK_APB3_I2C1 0x108
15 #define CLK_APB3_DAC 0x110
16 #define CLK_APB3_ADC0 0x118
17 #define CLK_APB3_ADC1 0x120
18 #define CLK_APB3_CAN0 0x128
19 #define CLK_APB1_BUS 0x200
20 #define CLK_APB1_MOTOCON_PWM 0x208
21 #define CLK_APB1_I2C0 0x210
22 #define CLK_APB1_I2S 0x218
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6dl-pinfunc.h13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
/freebsd/sys/contrib/device-tree/src/arm/calxeda/
H A Dhighbank.dts9 /memreserve/ 0x00000000 0x0001000;
19 #size-cells = <0>;
24 reg = <0x900>;
43 reg = <0x901>;
62 reg = <0x902>;
81 reg = <0x903>;
98 memory@0 {
101 reg = <0x00000000 0xff900000>;
105 ranges = <0x00000000 0x00000000 0xffffffff>;
109 reg = <0xfff00000 0x1000>;
[all …]
/freebsd/sys/contrib/device-tree/include/dt-bindings/pinctrl/
H A Dam33xx.h18 #define SLEWCTRL_FAST 0
30 #define PIN_OUTPUT_PULLDOWN 0
43 #define AM335X_PIN_OFFSET_MIN 0x0800U
45 #define AM335X_PIN_GPMC_AD0 0x800
46 #define AM335X_PIN_GPMC_AD1 0x804
47 #define AM335X_PIN_GPMC_AD2 0x808
48 #define AM335X_PIN_GPMC_AD3 0x80c
49 #define AM335X_PIN_GPMC_AD4 0x810
50 #define AM335X_PIN_GPMC_AD5 0x814
51 #define AM335X_PIN_GPMC_AD6 0x818
[all …]
/freebsd/sys/dev/firewire/
H A Diec68113.h40 #define oMPR 0x900
41 #define oPCR 0x904
42 #define iMPR 0x980
43 #define iPCR 0x984
47 uint8_t eoh0:1, /* 0 */
48 form0:1, /* 0 */
52 form0:1, /* 0 */
53 eoh0:1; /* 0 */
70 form1:1, /* 0 */
74 form1:1, /* 0 */
[all …]
/freebsd/sys/dev/pci/
H A Dpci_dw.h36 #define DW_PORT_LINK_CTRL 0x710
37 #define PORT_LINK_CAPABLE(n) (((n) & 0x3F) << 16)
38 #define PORT_LINK_CAPABLE_1 0x01
39 #define PORT_LINK_CAPABLE_2 0x03
40 #define PORT_LINK_CAPABLE_4 0x07
41 #define PORT_LINK_CAPABLE_8 0x0F
42 #define PORT_LINK_CAPABLE_16 0x1F
43 #define PORT_LINK_CAPABLE_32 0x3F
45 #define DW_GEN2_CTRL 0x80C
47 #define GEN2_CTRL_NUM_OF_LANES(n) (((n) & 0x3F) << 8)
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Dam437x-idk-evm.dts104 pinctrl-0 = <&gpio_keys_pins_default>;
106 switch-0 {
115 #clock-cells = <0>;
125 gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
176 AM4372_IOPAD(0x9b8, PIN_INPUT | MUX_MODE7) /* cam0_field.gpio4_2 */
182 AM4372_IOPAD(0x988, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
183 AM4372_IOPAD(0x98c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
189 AM4372_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE7)
190 AM4372_IOPAD(0x98c, PIN_INPUT_PULLDOWN | MUX_MODE7)
196 AM4372_IOPAD(0x9e
[all...]
H A Dam437x-sbc-t43.dts21 AM4372_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
22 AM4372_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
23 AM4372_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
24 AM4372_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
25 AM4372_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
26 AM4372_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
27 AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
28 AM4372_IOPAD(0x964, PIN_INPUT | MUX_MODE7) /* ecap0_in_pwm0_out.gpio0_7 */
34 AM4372_IOPAD(0x9b0, PIN_OUTPUT_PULLUP | MUX_MODE2) /* cam0 hd -> DSS DATA 23 */
35 AM4372_IOPAD(0x9b4, PIN_OUTPUT_PULLUP | MUX_MODE2)
[all …]
/freebsd/contrib/processor-trace/libipt/test/src/
H A Dptunit-mapped_section.c42 pt_msec_init(&msec, &sec, NULL, 0x2000ull, 0x100ull, 0x1000ull); in begin()
45 ptu_uint_eq(begin, 0x2000); in begin()
56 pt_msec_init(&msec, &sec, NULL, 0x2000ull, 0x100ull, 0x1000ull); in end()
59 ptu_uint_eq(end, 0x3000); in end()
70 pt_msec_init(&msec, &sec, NULL, 0x2000ull, 0x100ull, 0x1000ull); in offset()
73 ptu_uint_eq(offset, 0x100ull); in offset()
84 pt_msec_init(&msec, &sec, NULL, 0x2000ull, 0x100ull, 0x1000ull); in size()
87 ptu_uint_eq(size, 0x1000ull); in size()
99 asid.cr3 = 0xa00000ull; in asid()
100 asid.vmcs = 0xb00000ull; in asid()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/msm/
H A Ddpu-sc7280.yaml72 "^display-controller@[0-9a-f]+$":
128 port@0:
137 - port@0
174 reg = <0xae00000 0x1000>;
191 iommus = <&apps_smmu 0x900 0x402>;
196 reg = <0x0ae01000 0x8f000>,
197 <0x0aeb0000 0x2008>;
215 interrupts = <0>;
221 #size-cells = <0>;
223 port@0 {
[all …]
/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dsnps,dw-apb-ssi.yaml144 default: 0
163 "^.*@[0-9a-f]+$":
169 minimum: 0
185 reg = <0xfff00000 0x1000>;
187 #size-cells = <0>;
188 interrupts = <0 154 4>;
191 cs-gpios = <&gpio0 13 0>,
192 <&gpio0 14 0>;
203 reg = <0x1f040100 0x900>,
204 <0x1c000000 0x1000000>;
[all …]
/freebsd/sys/arm/include/
H A Dpl310.h37 #define PL310_CACHE_ID 0x000
38 #define CACHE_ID_RELEASE_SHIFT 0
39 #define CACHE_ID_RELEASE_MASK 0x3f
40 #define CACHE_ID_RELEASE_r0p0 0x00
41 #define CACHE_ID_RELEASE_r1p0 0x02
42 #define CACHE_ID_RELEASE_r2p0 0x04
43 #define CACHE_ID_RELEASE_r3p0 0x05
44 #define CACHE_ID_RELEASE_r3p1 0x06
45 #define CACHE_ID_RELEASE_r3p2 0x08
46 #define CACHE_ID_RELEASE_r3p3 0x09
[all …]

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