Lines Matching +full:0 +full:x900

36 #define	DW_PORT_LINK_CTRL		0x710
37 #define	 PORT_LINK_CAPABLE(n)			(((n) & 0x3F) << 16)
38 #define	 PORT_LINK_CAPABLE_1			0x01
39 #define	 PORT_LINK_CAPABLE_2			0x03
40 #define	 PORT_LINK_CAPABLE_4			0x07
41 #define	 PORT_LINK_CAPABLE_8			0x0F
42 #define	 PORT_LINK_CAPABLE_16			0x1F
43 #define	 PORT_LINK_CAPABLE_32			0x3F
45 #define	DW_GEN2_CTRL			0x80C
47 #define	 GEN2_CTRL_NUM_OF_LANES(n)		(((n) & 0x3F) << 8)
48 #define	 GEN2_CTRL_NUM_OF_LANES_1		0x01
49 #define	 GEN2_CTRL_NUM_OF_LANES_2		0x03
50 #define	 GEN2_CTRL_NUM_OF_LANES_4		0x07
51 #define	 GEN2_CTRL_NUM_OF_LANES_8		0x0F
52 #define	 GEN2_CTRL_NUM_OF_LANES_16		0x1F
53 #define	 GEN2_CTRL_NUM_OF_LANES_32		0x3F
55 #define DW_MSI_ADDR_LO			0x820
56 #define DW_MSI_ADDR_HI			0x824
57 #define DW_MSI_INTR0_ENABLE		0x828
58 #define DW_MSI_INTR0_MASK		0x82C
59 #define DW_MSI_INTR0_STATUS		0x830
61 #define	DW_MISC_CONTROL_1		0x8BC
62 #define	 DBI_RO_WR_EN				(1 << 0)
65 #define	DW_IATU_VIEWPORT			0x900
67 #define	 IATU_REGION_INDEX(x)			((x) & 0x7)
68 #define	DW_IATU_CTRL1			0x904
69 #define	 IATU_CTRL1_TYPE(x)			((x) & 0x1F)
70 #define	 IATU_CTRL1_TYPE_MEM			0x0
71 #define	 IATU_CTRL1_TYPE_IO			0x2
72 #define	 IATU_CTRL1_TYPE_CFG0			0x4
73 #define	 IATU_CTRL1_TYPE_CFG1			0x5
74 #define	DW_IATU_CTRL2			0x908
76 #define	DW_IATU_LWR_BASE_ADDR		0x90C
77 #define	DW_IATU_UPPER_BASE_ADDR		0x910
78 #define	DW_IATU_LIMIT_ADDR		0x914
79 #define	DW_IATU_LWR_TARGET_ADDR		0x918
80 #define	DW_IATU_UPPER_TARGET_ADDR	0x91C
83 #define	DW_IATU_UR_STEP			0x200
85 #define	 IATU_UR_CTRL1				0x00
86 #define	 IATU_UR_CTRL2				0x04
87 #define	 IATU_UR_LWR_BASE_ADDR			0x08
88 #define	 IATU_UR_UPPER_BASE_ADDR		0x0C
89 #define	 IATU_UR_LIMIT_ADDR			0x10
90 #define	 IATU_UR_LWR_TARGET_ADDR		0x14
91 #define	 IATU_UR_UPPER_TARGET_ADDR		0x18
93 #define	DW_DEFAULT_IATU_UR_DBI_OFFSET	0x300000
94 #define	DW_DEFAULT_IATU_UR_DBI_SIZE	0x1000