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/freebsd/sys/arm/allwinner/
H A Daw_machdep.h30 #define ALLWINNERSOC_A10 0x10000000
31 #define ALLWINNERSOC_A13 0x13000000
32 #define ALLWINNERSOC_A10S 0x10000001
33 #define ALLWINNERSOC_A20 0x20000000
34 #define ALLWINNERSOC_H3 0x30000000
35 #define ALLWINNERSOC_A31 0x31000000
36 #define ALLWINNERSOC_A31S 0x31000001
37 #define ALLWINNERSOC_A33 0x33000000
38 #define ALLWINNERSOC_A83T 0x83000000
40 #define ALLWINNERSOC_SUN4I 0x40000000
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/broadcom/stingray/
H A Dstingray-pcie.dtsi8 reg = <0 0x60400000 0 0x1000>;
11 bus-range = <0x0 0x1>;
16 ranges = <0x83000000 0 0x1000000
[all...]
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dmobiveil-pcie.txt49 reg = <0xa0000000 0x00001000>,
50 <0xb0000000 0x00010000>,
51 <0xff000000 0x00200000>,
52 <0xb0010000 0x00001000>;
60 bus-range = <0x00000000 0x000000ff>;
64 interrupts = < 0 89 4 >;
65 interrupt-map-mask = <0 0 0 7>;
66 interrupt-map = <0 0 0 0 &pci_express 0>,
67 <0 0 0 1 &pci_express 1>,
68 <0 0 0 2 &pci_express 2>,
[all …]
H A Drockchip-dw-pcie.yaml50 const: 0
89 reg = <0x3 0xc0800000 0x0 0x390000>,
90 <0x0 0xfe280000 0x0 0x10000>,
91 <0x3 0x80000000 0x0 0x100000>;
93 bus-range = <0x20 0x2f>;
109 msi-map = <0x2000 &its 0x2000 0x1000>;
114 ranges = <0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000>,
115 <0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>;
123 #address-cells = <0>;
H A Drockchip,rk3399-pcie.yaml61 const: 0
98 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
99 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
100 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
103 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
104 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
106 msi-map = <0x0 &its 0x0 0x1000>;
107 reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>;
118 pinctrl-0 = <&pcie_clkreq>;
120 interrupt-map-mask = <0 0 0 7>;
[all …]
H A Dapple,pcie.yaml114 reg = <0x6 0x90000000 0x0 0x1000000>,
115 <0x6 0x80000000 0x0 0x100000>,
116 <0x6 0x81000000 0x0 0x4000>,
117 <0x6 0x82000000 0x0 0x4000>,
118 <0x6 0x83000000 0x0 0x4000>;
130 iommu-map = <0x100 &dart0 1 1>,
131 <0x200 &dart1 1 1>,
132 <0x300 &dart2 1 1>;
133 iommu-map-mask = <0xff00>;
135 bus-range = <0 3>;
[all …]
H A Drockchip-pcie-host.txt38 - pinctrl-0: The "default" pinctrl state
51 where N ranges from 0 to 3.
75 address. The value must be 0.
89 bus-range = <0x0 0x1>;
90 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
91 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
92 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
98 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
99 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
101 msi-map = <0x0 &its 0x0 0x1000>;
[all …]
H A Dmediatek-pcie.txt32 where N starting from 0 to one less than the number of root ports.
80 reg = <0 0x1a000000 0 0x1000>;
88 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
89 <0 0x1a142000 0 0x1000>, /* Port0 registers */
90 <0 0x1a143000 0 0x1000>, /* Port1 registers */
91 <0 0x1a144000 0 0x1000>; /* Port2 registers */
96 interrupt-map-mask = <0xf800 0 0 0>;
97 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
98 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
99 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
[all …]
/freebsd/contrib/arm-optimized-routines/math/aarch64/advsimd/
H A Dexpf_1u.c19 .ln2_hi = 0x1.62e4p-1f,
20 .ln2_lo = 0x1.7f7d1cp-20f,
21 .shift = V4 (0x1.8p23f),
22 .inv_ln2 = V4 (0x1.715476p+0f),
23 .exponent_bias = V4 (0x3f800000),
26 .special_offset = V4 (0x83000000),
27 .special_bias = V4 (0x7f000000),
29 .c0 = 0x1.6a6000p-10f,
30 .c1 = V4 (0x1.12718ep-7f),
31 .c2 = V4 (0x1.555af0p-5f),
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/broadcom/northstar2/
H A Dns2.dtsi33 /memreserve/ 0x81000000 0x00200000;
46 #size-cells = <0>;
48 A57_0: cpu@0 {
51 reg = <0 0>;
59 reg = <0 1>;
67 reg = <0 2>;
75 reg = <0 3>;
80 CLUSTER0_L2: l2-cache@0 {
94 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
96 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dmsm8956-sony-xperia-loire.dtsi16 qcom,msm-id = <266 0x10001>; /* MSM8956 v1.1 */
17 qcom,board-id = <8 0>;
32 reg = <0x0 0x83000000 0x0 0x2800000>;
37 reg = <0 0x57f00000 0 0x100000>;
38 record-size = <0x20000>;
39 console-size = <0x40000>;
40 ftrace-size = <0x20000>;
41 pmsg-size = <0x20000>;
111 /* Cluster 0 supply */
274 gpio-reserved-ranges = <0 4>;
/freebsd/sys/contrib/device-tree/src/arm64/apple/
H A Dt600x-die0.dtsi3 * Devices used on die 0 on the Apple T6002 "M1 Ultra" SoC and present on
12 reg = <0x2 0x8e03c000 0x0 0x14000>;
21 reg = <0x2 0x8e100000 0x0 0xc000>,
22 <0x2 0x8e10c000 0x0 0x4>;
29 reg = <0x2 0x90820000 0x0 0x4000>;
33 gpio-ranges = <&pinctrl_smc 0 0 30>;
39 interrupts = <AIC_IRQ 0 743 IRQ_TYPE_LEVEL_HIGH>,
40 <AIC_IRQ 0 744 IRQ_TYPE_LEVEL_HIGH>,
41 <AIC_IRQ 0 745 IRQ_TYPE_LEVEL_HIGH>,
42 <AIC_IRQ 0 746 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Dt8103.dtsi23 #size-cells = <0>;
57 cpu_e0: cpu@0 {
60 reg = <0x0 0x0>;
62 cpu-release-addr = <0 0>; /* To be filled by loader */
67 i-cache-size = <0x20000>;
68 d-cache-size = <0x10000>;
74 reg = <0x0 0x1>;
76 cpu-release-addr = <0 0>; /* To be filled by loader */
81 i-cache-size = <0x20000>;
82 d-cache-size = <0x10000>;
[all …]
H A Dt8112.dtsi24 #size-cells = <0>;
58 cpu_e0: cpu@0 {
61 reg = <0x0 0x0>;
63 cpu-release-addr = <0 0>; /* To be filled by loader */
68 i-cache-size = <0x20000>;
69 d-cache-size = <0x10000>;
75 reg = <0x0 0x1>;
77 cpu-release-addr = <0 0>; /* To be filled by loader */
82 i-cache-size = <0x20000>;
83 d-cache-size = <0x10000>;
[all …]
/freebsd/sys/arm64/qoriq/
H A Dqoriq_therm.c51 #define TMU_TMR 0x00
52 #define TMU_TSR 0x04
53 #define TMUV1_TMTMIR 0x08
54 #define TMUV2_TMSR 0x08
55 #define TMUV2_TMTMIR 0x0C
56 #define TMU_TIER 0x20
57 #define TMU_TTCFGR 0x80
58 #define TMU_TSCFGR 0x84
59 #define TMU_TRITSR(x) (0x100 + (16 * (x)))
61 #define TMUV2_TMSAR(x) (0x304 + (16 * (x)))
[all …]
/freebsd/sys/contrib/dev/rtw88/
H A Drtw8822b_table.c10 0x029, 0x000000F9,
11 0x420, 0x00000080,
12 0x421, 0x0000001F,
13 0x428, 0x0000000A,
14 0x429, 0x00000010,
15 0x430, 0x00000000,
16 0x431, 0x00000000,
17 0x432, 0x00000000,
18 0x433, 0x00000001,
19 0x434, 0x00000004,
[all …]
H A Drtw8822c_table.c16 0x83000000, 0x00000000, 0x40000000, 0x00000000,
17 0x1D90, 0x300001FF,
18 0x1D90, 0x300101FE,
19 0x1D9
[all...]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7996/
H A Dregs.h73 #define MT_RRO_TOP_BASE 0xA000
76 #define MT_RRO_BA_BITMAP_BASE0 MT_RRO_TOP(0x8)
77 #define MT_RRO_BA_BITMAP_BASE1 MT_RRO_TOP(0xC)
78 #define WF_RRO_AXI_MST_CFG MT_RRO_TOP(0xB8)
80 #define MT_RRO_ADDR_ARRAY_BASE1 MT_RRO_TOP(0x34)
83 #define MT_RRO_IND_CMD_SIGNATURE_BASE0 MT_RRO_TOP(0x38)
84 #define MT_RRO_IND_CMD_SIGNATURE_BASE1 MT_RRO_TOP(0x3C)
85 #define MT_RRO_IND_CMD_0_CTRL0 MT_RRO_TOP(0x40)
88 #define MT_RRO_PARTICULAR_CFG0 MT_RRO_TOP(0x5C)
89 #define MT_RRO_PARTICULAR_CFG1 MT_RRO_TOP(0x60)
[all …]
/freebsd/sys/contrib/openzfs/module/icp/asm-x86_64/aes/
H A Daestab2.h50 0x00000001, 0x00000002, 0x00000004, 0x00000008,
51 0x00000010, 0x00000020, 0x00000040, 0x00000080,
52 0x0000001b, 0x00000036
58 0x00000063, 0x0000007c, 0x00000077, 0x0000007b,
59 0x000000f2, 0x0000006b, 0x0000006f, 0x000000c5,
60 0x00000030, 0x00000001, 0x00000067, 0x0000002b,
61 0x000000fe, 0x000000d7, 0x000000ab, 0x00000076,
62 0x000000ca, 0x00000082, 0x000000c9, 0x0000007d,
63 0x000000fa, 0x00000059, 0x00000047, 0x000000f0,
64 0x000000ad, 0x000000d4, 0x000000a2, 0x000000af,
[all …]
/freebsd/sys/contrib/device-tree/src/arm/mediatek/
H A Dmt7623.dtsi73 #size-cells = <0>;
76 cpu0: cpu@0 {
79 reg = <0x0>;
91 reg = <0x1>;
103 reg = <0x2>;
115 reg = <0x3>;
137 #clock-cells = <0>;
142 #clock-cells = <0>;
147 clk26m: oscillator-0 {
149 #clock-cells = <0>;
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7915/
H A Dregs.h130 #define MT_MCU_WFDMA0_BASE 0x2000
133 #define MT_MCU_WFDMA0_DUMMY_CR MT_MCU_WFDMA0(0x120)
136 #define MT_MCU_WFDMA1_BASE 0x3000
140 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)
146 #define MT_PLE_BASE 0x820c0000
149 #define MT_PLE_HOST_RPT0 MT_PLE(0x030)
154 #define MT_FL_Q2_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL) + 0x8)
155 #define MT_FL_Q3_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL) + 0xc)
165 #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2))
167 #define MT_PSE_BASE 0x820c8000
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Decore_init_values.h35 0x00030003, 0xffff0000, /* if phase != 'engine', skip 3 ops (no DMAE) */
36 0x00020002, 0x00020000, /* if mode != '!asic', skip 2 ops */
37 0x0280c201, 0x00000000, /* write 0x0 to address 0x50184 */
38 0x02810201, 0x00000000, /* write 0x0 to address 0x50204 */
40 0x00110003, 0xffff0000, /* if phase != 'engine', skip 17 ops (no DMAE) */
41 0x00030002, 0x00020000, /* if mode != '!asic', skip 3 ops */
42 0x0048c201, 0x00000000, /* write 0x0 to address 0x9184 */
43 0x0048d201, 0x00000000, /* write 0x0 to address 0x91a4 */
44 0x004ba601, 0x00000001, /* write 0x1 to address 0x974c */
45 0x00020002, 0x00be0000, /* if mode != '(!asic)&bb', skip 2 ops */
[all …]
/freebsd/tools/test/iconv/ref/
H A DUTF-32BE-rev1 0x00 = 0x00000000
2 0x01 = 0x01000000
3 0x02 = 0x02000000
4 0x03 = 0x03000000
5 0x04 = 0x04000000
6 0x05 = 0x05000000
7 0x06 = 0x06000000
8 0x07 = 0x07000000
9 0x08 = 0x08000000
10 0x09 = 0x09000000
[all …]