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/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dsdhci-msm.txt11 For SDCC version 5.0.0, MCI registers are removed from SDCC
47 - pinctrl-0: Should specify pin control groups used for this controller.
84 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
85 interrupts = <0 123 0>;
93 pinctrl-0 = <&sdc1_clk &sdc1_cmd &sdc1_data>;
101 qcom,dll-config = <0x000f642c>;
102 qcom,ddr-config = <0x80040868>;
107 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
108 interrupts = <0 125 0>;
110 cd-gpios = <&msmgpio 62 0x1>;
[all …]
H A Dsdhci-msm.yaml112 pinctrl-0:
163 '^opp-?[0-9]+$':
225 reg = <0 0x08804000 0 0x1000>;
235 iommus = <&apps_smmu 0x4a0 0x0>;
236 qcom,dll-config = <0x0007642c>;
237 qcom,ddr-config = <0x8004086
[all...]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dqcm2290.dtsi30 #clock-cells = <0>;
36 #clock-cells = <0>;
42 #size-cells = <0>;
44 CPU0: cpu@0 {
47 reg = <0x0 0x0>;
48 clocks = <&cpufreq_hw 0>;
53 qcom,freq-domain = <&cpufreq_hw 0>;
66 reg = <0x0 0x
[all...]
H A Dsm6350.dtsi31 #clock-cells = <0>;
39 #clock-cells = <0>;
45 #size-cells = <0>;
47 CPU0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
80 reg = <0x0 0x10
[all...]
H A Dqdu1000.dtsi24 #size-cells = <0>;
26 CPU0: cpu@0 {
29 reg = <0x0 0x0>;
30 clocks = <&cpufreq_hw 0>;
34 qcom,freq-domains = <&cpufreq_hw 0>;
52 reg = <0x0 0x100>;
53 clocks = <&cpufreq_hw 0>;
57 qcom,freq-domains = <&cpufreq_hw 0>;
[all...]
H A Dsm6375.dtsi27 #clock-cells = <0>;
33 #clock-cells = <0>;
39 #size-cells = <0>;
41 CPU0: cpu@0 {
44 reg = <0x0 0x0>;
45 clocks = <&cpufreq_hw 0>;
48 qcom,freq-domain = <&cpufreq_hw 0>;
70 reg = <0x0 0x10
[all...]
H A Dsm6115.dtsi29 #clock-cells = <0>;
34 #clock-cells = <0>;
40 #size-cells = <0>;
42 CPU0: cpu@0 {
45 reg = <0x0 0x0>;
46 clocks = <&cpufreq_hw 0>;
51 qcom,freq-domain = <&cpufreq_hw 0>;
64 reg = <0x0 0x
[all...]
H A Dsm8150.dtsi32 #clock-cells = <0>;
39 #clock-cells = <0>;
47 #size-cells = <0>;
49 CPU0: cpu@0 {
52 reg = <0x0 0x0>;
53 clocks = <&cpufreq_hw 0>;
58 qcom,freq-domain = <&cpufreq_hw 0>;
60 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
[all...]
H A Dsm8550.dtsi38 #clock-cells = <0>;
43 #clock-cells = <0>;
47 #clock-cells = <0>;
55 #clock-cells = <0>;
64 #clock-cells = <0>;
70 #size-cells = <0>;
72 CPU0: cpu@0 {
75 reg = <0 0>;
76 clocks = <&cpufreq_hw 0>;
[all...]
H A Dsm8250.dtsi82 #clock-cells = <0>;
90 #clock-cells = <0>;
96 #size-cells = <0>;
98 CPU0: cpu@0 {
101 reg = <0x0 0x0>;
102 clocks = <&cpufreq_hw 0>;
109 qcom,freq-domain = <&cpufreq_hw 0>;
111 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
[all...]
H A Dsc7280.dtsi80 #clock-cells = <0>;
86 #clock-cells = <0>;
97 reg = <0x0 0x004cd000 0x0 0x1000>;
101 reg = <0x0 0x80000000 0x0 0x60000
[all...]