Searched +full:0 +full:x7e00b200 (Results 1 – 4 of 4) sorted by relevance
24 Bank 0:25 0: ARM_TIMER35 0: TIMER069 0: HOSTPORT116 The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic121 are 0..7 for bank 0, and 0..31 for bank 1.151 reg = <0x7e00b200 0x200>;158 reg = <0x7e00b200 0x200>;
13 reg = <0x7e007000 0xf00>;49 brcm,dma-channel-mask = <0x7f35>;54 reg = <0x7e00b200 0x200>;63 reg = <0x7e100000 0x114>,64 <0x7e00a000 0x24>;76 reg = <0x7e104000 0x10>;82 reg = <0x7e206000 0x100>;88 reg = <0x7e207000 0x100>;94 reg = <0x7e212000 0x8>;96 #thermal-sensor-cells = <0>;[all …]
8 ranges = <0x7e000000 0x3f000000 0x1000000>,9 <0x40000000 0x40000000 0x00001000>;10 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;14 reg = <0x40000000 0x100>;30 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI39 #size-cells = <0>;49 cpu0: cpu@0 {52 reg = <0>;54 cpu-release-addr = <0x0 0x000000d8>;55 d-cache-size = <0x8000>;[all …]
9 ranges = <0x7e000000 0x3f000000 0x1000000>,10 <0x40000000 0x40000000 0x00001000>;11 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;15 reg = <0x40000000 0x100>;31 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI40 #size-cells = <0>;51 v7_cpu0: cpu@0 {54 reg = <0xf00>;56 d-cache-size = <0x8000>;59 i-cache-size = <0x8000>;[all …]