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/linux/drivers/gpu/drm/radeon/
H A Dr600_reg.h31 #define R600_PCIE_PORT_INDEX 0x0038
32 #define R600_PCIE_PORT_DATA 0x003c
34 #define R600_RCU_INDEX 0x0100
35 #define R600_RCU_DATA 0x0104
37 #define R600_UVD_CTX_INDEX 0xf4a0
38 #define R600_UVD_CTX_DATA 0xf4a4
40 #define R600_MC_VM_FB_LOCATION 0x2180
41 #define R600_MC_FB_BASE_MASK 0x0000FFFF
42 #define R600_MC_FB_BASE_SHIFT 0
43 #define R600_MC_FB_TOP_MASK 0xFFFF0000
[all …]
H A Drv770d.h35 #define R7XX_MAX_BACKENDS_MASK 0xff
37 #define R7XX_MAX_SIMDS_MASK 0xffff
39 #define R7XX_MAX_PIPES_MASK 0xff
42 #define CG_UPLL_FUNC_CNTL 0x718
43 # define UPLL_RESET_MASK 0x00000001
44 # define UPLL_SLEEP_MASK 0x00000002
45 # define UPLL_BYPASS_EN_MASK 0x00000004
46 # define UPLL_CTLREQ_MASK 0x00000008
48 # define UPLL_REF_DIV_MASK 0x003F0000
49 # define UPLL_CTLACK_MASK 0x40000000
[all …]
H A Devergreen_reg.h28 #define TN_SMC_IND_INDEX_0 0x200
29 #define TN_SMC_IND_DATA_0 0x204
32 #define EVERGREEN_PIF_PHY0_INDEX 0x8
33 #define EVERGREEN_PIF_PHY0_DATA 0xc
34 #define EVERGREEN_PIF_PHY1_INDEX 0x10
35 #define EVERGREEN_PIF_PHY1_DATA 0x14
36 #define EVERGREEN_MM_INDEX_HI 0x18
38 #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0x310
39 #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0x324
40 #define EVERGREEN_D3VGA_CONTROL 0x3e0
[all …]
/linux/Documentation/devicetree/bindings/soc/qcom/
H A Dqcom,pbs.yaml37 pmic@0 {
38 reg = <0x0 SPMI_USID>;
40 #size-cells = <0>;
44 reg = <0x7400>;
/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Ddcore0_tpc0_eml_busmon_0_regs.h23 #define mmDCORE0_TPC0_EML_BUSMON_0_CR 0x7000
25 #define mmDCORE0_TPC0_EML_BUSMON_0_REG_RESET 0x7004
27 #define mmDCORE0_TPC0_EML_BUSMON_0_INT_CLR 0x7008
29 #define mmDCORE0_TPC0_EML_BUSMON_0_TRIG_TH 0x700C
31 #define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S0 0x7020
33 #define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S0 0x7024
35 #define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_E0 0x7028
37 #define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_E0 0x702C
39 #define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S1 0x7030
41 #define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S1 0x7034
[all …]
/linux/drivers/media/i2c/
H A Dhi847.c25 #define HI847_REG_CHIP_ID 0x0716
26 #define HI847_CHIP_ID 0x0847
28 #define HI847_REG_MODE_SELECT 0x0B00
29 #define HI847_MODE_STANDBY 0x0000
30 #define HI847_MODE_STREAMING 0x0100
32 #define HI847_REG_MODE_TG 0x027E
33 #define HI847_REG_MODE_TG_ENABLE 0x0100
34 #define HI847_REG_MODE_TG_DISABLE 0x0000
37 #define HI847_REG_FLL 0x020E
38 #define HI847_FLL_30FPS 0x0B51
[all …]
H A Dhi556.c26 #define HI556_REG_CHIP_ID 0x0f16
27 #define HI556_CHIP_ID 0x0556
29 #define HI556_REG_MODE_SELECT 0x0a00
30 #define HI556_MODE_STANDBY 0x0000
31 #define HI556_MODE_STREAMING 0x0100
34 #define HI556_REG_FLL 0x0006
35 #define HI556_FLL_30FPS 0x0814
36 #define HI556_FLL_30FPS_MIN 0x0814
37 #define HI556_FLL_MAX 0x7fff
40 #define HI556_REG_LLP 0x0008
[all …]
/linux/arch/powerpc/include/asm/
H A Dtsi108.h18 #define TSI108_REG_SIZE (0x10000)
21 #define TSI108_HLP_SIZE 0x1000
22 #define TSI108_PCI_SIZE 0x1000
23 #define TSI108_CLK_SIZE 0x1000
24 #define TSI108_PB_SIZE 0x1000
25 #define TSI108_SD_SIZE 0x1000
26 #define TSI108_DMA_SIZE 0x1000
27 #define TSI108_ETH_SIZE 0x1000
28 #define TSI108_I2C_SIZE 0x400
29 #define TSI108_MPIC_SIZE 0x400
[all …]
/linux/drivers/gpu/drm/hisilicon/kirin/
H A Dkirin_ade_reg.h15 #define ADE_CTRL 0x0004
16 #define FRM_END_START_OFST 0
18 #define AUTO_CLK_GATE_EN_OFST 0
19 #define AUTO_CLK_GATE_EN BIT(0)
20 #define ADE_DISP_SRC_CFG 0x0018
21 #define ADE_CTRL1 0x008C
22 #define ADE_EN 0x0100
23 #define ADE_DISABLE 0
26 #define ADE_SOFT_RST_SEL(x) (0x0078 + (x) * 0x4)
27 #define ADE_RELOAD_DIS(x) (0x00AC + (x) * 0x4)
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dpmi632.dtsi20 hysteresis = <0>;
26 hysteresis = <0>;
32 hysteresis = <0>;
43 reg = <0x2 SPMI_USID>;
45 #size-cells = <0>;
49 reg = <0x1100>;
55 reg = <0x1500>;
56 interrupts = <0x2 0x15 0x00 IRQ_TYPE_EDGE_RISING>,
57 <0x2 0x15 0x01 IRQ_TYPE_EDGE_BOTH>,
58 <0x2 0x15 0x02 IRQ_TYPE_EDGE_RISING>,
[all …]
/linux/arch/mips/include/uapi/asm/
H A Dioctls.h15 #define TCGETA 0x5401
16 #define TCSETA 0x5402 /* Clashes with SNDCTL_TMR_START sound ioctl */
17 #define TCSETAW 0x5403
18 #define TCSETAF 0x5404
20 #define TCSBRK 0x5405
21 #define TCXONC 0x5406
22 #define TCFLSH 0x5407
24 #define TCGETS 0x540d
25 #define TCSETS 0x540e
26 #define TCSETSW 0x540f
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv10.c34 u32 pipe_0x0000[0x040/4];
35 u32 pipe_0x0040[0x010/4];
36 u32 pipe_0x0200[0x0c0/4];
37 u32 pipe_0x4400[0x080/4];
38 u32 pipe_0x6400[0x3b0/4];
39 u32 pipe_0x6800[0x2f0/4];
40 u32 pipe_0x6c00[0x030/4];
41 u32 pipe_0x7000[0x130/4];
42 u32 pipe_0x7400[0x0c0/4];
43 u32 pipe_0x7800[0x0c0/4];
[all …]
/linux/drivers/dma/ti/
H A Dk3-psil-j7200.c64 PSIL_PDMA_MCASP(0x4400),
65 PSIL_PDMA_MCASP(0x4401),
66 PSIL_PDMA_MCASP(0x4402),
68 PSIL_PDMA_XY_PKT(0x4600),
69 PSIL_PDMA_XY_PKT(0x4601),
70 PSIL_PDMA_XY_PKT(0x4602),
71 PSIL_PDMA_XY_PKT(0x4603),
72 PSIL_PDMA_XY_PKT(0x4604),
73 PSIL_PDMA_XY_PKT(0x4605),
74 PSIL_PDMA_XY_PKT(0x4606),
[all …]
H A Dk3-psil-j721s2.c71 PSIL_PDMA_MCASP(0x4400),
72 PSIL_PDMA_MCASP(0x4401),
73 PSIL_PDMA_MCASP(0x4402),
74 PSIL_PDMA_MCASP(0x4403),
75 PSIL_PDMA_MCASP(0x4404),
77 PSIL_PDMA_XY_PKT(0x4600),
78 PSIL_PDMA_XY_PKT(0x4601),
79 PSIL_PDMA_XY_PKT(0x4602),
80 PSIL_PDMA_XY_PKT(0x4603),
81 PSIL_PDMA_XY_PKT(0x4604),
[all …]
H A Dk3-psil-j784s4.c71 PSIL_PDMA_MCASP(0x4400),
72 PSIL_PDMA_MCASP(0x4401),
73 PSIL_PDMA_MCASP(0x4402),
74 PSIL_PDMA_MCASP(0x4403),
75 PSIL_PDMA_MCASP(0x4404),
77 PSIL_PDMA_XY_PKT(0x4600),
78 PSIL_PDMA_XY_PKT(0x4601),
79 PSIL_PDMA_XY_PKT(0x4602),
80 PSIL_PDMA_XY_PKT(0x4603),
81 PSIL_PDMA_XY_PKT(0x4604),
[all …]
H A Dk3-psil-j721e.c72 PSIL_SA2UL(0x4000, 0),
73 PSIL_SA2UL(0x4001, 0),
74 PSIL_SA2UL(0x4002, 0),
75 PSIL_SA2UL(0x4003, 0),
77 PSIL_ETHERNET(0x4100),
78 PSIL_ETHERNET(0x4101),
79 PSIL_ETHERNET(0x4102),
80 PSIL_ETHERNET(0x4103),
82 PSIL_ETHERNET(0x4200),
83 PSIL_ETHERNET(0x4201),
[all …]
/linux/sound/soc/codecs/
H A Drt711.h32 #define RT711_AUDIO_FUNCTION_GROUP 0x01
33 #define RT711_DAC_OUT2 0x03
34 #define RT711_ADC_IN1 0x09
35 #define RT711_ADC_IN2 0x08
36 #define RT711_DMIC1 0x12
37 #define RT711_DMIC2 0x13
38 #define RT711_MIC2 0x19
39 #define RT711_LINE1 0x1a
40 #define RT711_LINE2 0x1b
41 #define RT711_BEEP 0x1d
[all …]
/linux/drivers/cpufreq/
H A Dsun50i-cpufreq-nvmem.c22 #define NVMEM_MASK 0x7
45 return 0; in sun50i_h6_efuse_xlate()
59 * returned speedbin index is 4 -> 0/2 -> 3 -> 1, from worst to best.
60 * 0 and 2 seem identical from the OPP tables' point of view.
65 u32 value = 0; in sun50i_h616_efuse_xlate()
67 switch (speedbin & 0xffff) { in sun50i_h616_efuse_xlate()
68 case 0x2000: in sun50i_h616_efuse_xlate()
69 value = 0; in sun50i_h616_efuse_xlate()
71 case 0x2400: in sun50i_h616_efuse_xlate()
72 case 0x7400: in sun50i_h616_efuse_xlate()
[all …]
/linux/drivers/net/wireless/ath/ath10k/
H A Dcoredump.c19 {0x800, 0x810},
20 {0x820, 0x82C},
21 {0x830, 0x8F4},
22 {0x90C, 0x91C},
23 {0xA14, 0xA18},
24 {0xA84, 0xA94},
25 {0xAA8, 0xAD4},
26 {0xADC, 0xB40},
27 {0x1000, 0x10A4},
28 {0x10BC, 0x111C},
[all …]
/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt7629.c12 MTK_PIN(_number, _name, 0, _eint_n, DRV_GRP1)
15 PIN_FIELD(0, 78, 0x300, 0x10, 0, 4),
19 PIN_FIELD(0, 78, 0x0, 0x10, 0, 1),
23 PIN_FIELD(0, 78, 0x200, 0x10, 0, 1),
27 PIN_FIELD(0, 78, 0x100, 0x10, 0, 1),
31 PIN_FIELD(0, 10, 0x1000, 0x10, 0, 1),
32 PIN_FIELD(11, 18, 0x2000, 0x10, 0, 1),
33 PIN_FIELD(19, 32, 0x3000, 0x10, 0, 1),
34 PIN_FIELD(33, 48, 0x4000, 0x10, 0, 1),
35 PIN_FIELD(49, 50, 0x5000, 0x10, 0, 1),
[all …]
/linux/drivers/media/dvb-frontends/
H A Dstv6111.c37 { 2572, 0 },
73 { 1548, 0 },
109 { 4870, 0x3000 },
110 { 4850, 0x3C00 },
111 { 4800, 0x4500 },
112 { 4750, 0x4800 },
113 { 4700, 0x4B00 },
114 { 4650, 0x4D00 },
115 { 4600, 0x4F00 },
116 { 4550, 0x5100 },
[all …]
/linux/drivers/scsi/qla2xxx/
H A Dqla_dbg.c13 * | Module Init and Probe | 0x0199 | |
14 * | Mailbox commands | 0x1206 | 0x11a5-0x11ff |
15 * | Device Discovery | 0x2134 | 0x2112-0x2115 |
16 * | | | 0x2127-0x2128 |
17 * | Queue Command and IO tracing | 0x3074 | 0x300b |
18 * | | | 0x3027-0x3028 |
19 * | | | 0x303d-0x3041 |
20 * | | | 0x302e,0x3033 |
21 * | | | 0x3036,0x3038 |
22 * | | | 0x303a |
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-j721e-mcu-wakeup.dtsi19 reg = <0x00 0x44083000 0x0 0x1000>;
41 ranges = <0x0 0x0 0x40f00000 0x20000>;
45 reg = <0x200 0x8>;
50 reg = <0x4040 0x4>;
59 ranges = <0x0 0x00 0x43000000 0x20000>;
63 reg = <0x14 0x4>;
69 /* Proxy 0 addressing */
70 reg = <0x00 0x4301c000 0x00 0x178>;
73 pinctrl-single,function-mask = <0xffffffff>;
79 reg = <0x00 0x40f04200 0x00 0x28>;
[all …]
H A Dk3-j7200-mcu-wakeup.dtsi19 reg = <0x00 0x44083000 0x00 0x1000>;
40 reg = <0x00 0x40400000 0x00 0x400>;
53 reg = <0x00 0x40410000 0x00 0x400>;
57 assigned-clocks = <&k3_clks 71 1>, <&k3_clks 308 0>;
66 reg = <0x00 0x40420000 0x00 0x400>;
79 reg = <0x00 0x40430000 0x00 0x400>;
83 assigned-clocks = <&k3_clks 73 1>, <&k3_clks 309 0>;
92 reg = <0x00 0x40440000 0x00 0x400>;
105 reg = <0x00 0x40450000 0x00 0x400>;
109 assigned-clocks = <&k3_clks 75 1>, <&k3_clks 310 0>;
[all …]
H A Dk3-j784s4-mcu-wakeup.dtsi20 reg = <0x00 0x44083000 0x00 0x1000>;
46 ranges = <0x0 0x00 0x43000000 0x20000>;
51 reg = <0x14 0x4>;
59 reg = <0x00 0x43600000 0x00 0x10000>,
60 <0x00 0x44880000 0x00 0x20000>,
61 <0x00 0x44860000 0x00 0x20000>;
72 reg = <0x00 0x41c00000 0x00 0x100000>;
73 ranges = <0x00 0x00 0x41c00000 0x100000>;
80 /* Proxy 0 addressing */
81 reg = <0x00 0x4301c000 0x00 0x034>;
[all …]

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