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/linux/drivers/gpu/drm/radeon/
H A Dr600_reg.h31 #define R600_PCIE_PORT_INDEX 0x0038
32 #define R600_PCIE_PORT_DATA 0x003c
34 #define R600_RCU_INDEX 0x0100
35 #define R600_RCU_DATA 0x0104
37 #define R600_UVD_CTX_INDEX 0xf4a0
38 #define R600_UVD_CTX_DATA 0xf4a4
40 #define R600_MC_VM_FB_LOCATION 0x2180
41 #define R600_MC_FB_BASE_MASK 0x0000FFFF
42 #define R600_MC_FB_BASE_SHIFT 0
43 #define R600_MC_FB_TOP_MASK 0xFFFF0000
[all …]
H A Drv770d.h35 #define R7XX_MAX_BACKENDS_MASK 0xff
37 #define R7XX_MAX_SIMDS_MASK 0xffff
39 #define R7XX_MAX_PIPES_MASK 0xff
42 #define CG_UPLL_FUNC_CNTL 0x718
43 # define UPLL_RESET_MASK 0x00000001
44 # define UPLL_SLEEP_MASK 0x00000002
45 # define UPLL_BYPASS_EN_MASK 0x00000004
46 # define UPLL_CTLREQ_MASK 0x00000008
48 # define UPLL_REF_DIV_MASK 0x003F0000
49 # define UPLL_CTLACK_MASK 0x40000000
[all …]
H A Devergreen_reg.h28 #define TN_SMC_IND_INDEX_0 0x200
29 #define TN_SMC_IND_DATA_0 0x204
32 #define EVERGREEN_PIF_PHY0_INDEX 0x8
33 #define EVERGREEN_PIF_PHY0_DATA 0xc
34 #define EVERGREEN_PIF_PHY1_INDEX 0x10
35 #define EVERGREEN_PIF_PHY1_DATA 0x14
36 #define EVERGREEN_MM_INDEX_HI 0x18
38 #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0x310
39 #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0x324
40 #define EVERGREEN_D3VGA_CONTROL 0x3e0
[all …]
/linux/Documentation/devicetree/bindings/soc/qcom/
H A Dqcom,pbs.yaml37 pmic@0 {
38 reg = <0x0 SPMI_USID>;
40 #size-cells = <0>;
44 reg = <0x7400>;
/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Ddcore0_tpc0_eml_busmon_0_regs.h23 #define mmDCORE0_TPC0_EML_BUSMON_0_CR 0x7000
25 #define mmDCORE0_TPC0_EML_BUSMON_0_REG_RESET 0x7004
27 #define mmDCORE0_TPC0_EML_BUSMON_0_INT_CLR 0x7008
29 #define mmDCORE0_TPC0_EML_BUSMON_0_TRIG_TH 0x700C
31 #define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S0 0x7020
33 #define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S0 0x7024
35 #define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_E0 0x7028
37 #define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_E0 0x702C
39 #define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S1 0x7030
41 #define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S1 0x7034
[all …]
/linux/arch/powerpc/include/asm/
H A Dtsi108.h18 #define TSI108_REG_SIZE (0x10000)
21 #define TSI108_HLP_SIZE 0x1000
22 #define TSI108_PCI_SIZE 0x1000
23 #define TSI108_CLK_SIZE 0x1000
24 #define TSI108_PB_SIZE 0x1000
25 #define TSI108_SD_SIZE 0x1000
26 #define TSI108_DMA_SIZE 0x1000
27 #define TSI108_ETH_SIZE 0x1000
28 #define TSI108_I2C_SIZE 0x400
29 #define TSI108_MPIC_SIZE 0x400
[all …]
/linux/drivers/gpu/drm/hisilicon/kirin/
H A Dkirin_ade_reg.h15 #define ADE_CTRL 0x0004
16 #define FRM_END_START_OFST 0
18 #define AUTO_CLK_GATE_EN_OFST 0
19 #define AUTO_CLK_GATE_EN BIT(0)
20 #define ADE_DISP_SRC_CFG 0x0018
21 #define ADE_CTRL1 0x008C
22 #define ADE_EN 0x0100
23 #define ADE_DISABLE 0
26 #define ADE_SOFT_RST_SEL(x) (0x0078 + (x) * 0x4)
27 #define ADE_RELOAD_DIS(x) (0x00AC + (x) * 0x4)
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dpmi632.dtsi20 hysteresis = <0>;
26 hysteresis = <0>;
32 hysteresis = <0>;
43 reg = <0x2 SPMI_USID>;
45 #size-cells = <0>;
49 reg = <0x1100>;
55 reg = <0x1500>;
56 interrupts = <0x2 0x15 0x00 IRQ_TYPE_EDGE_RISING>,
57 <0x2 0x15 0x01 IRQ_TYPE_EDGE_BOTH>,
58 <0x2 0x15 0x02 IRQ_TYPE_EDGE_RISING>,
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv10.c34 u32 pipe_0x0000[0x040/4];
35 u32 pipe_0x0040[0x010/4];
36 u32 pipe_0x0200[0x0c0/4];
37 u32 pipe_0x4400[0x080/4];
38 u32 pipe_0x6400[0x3b0/4];
39 u32 pipe_0x6800[0x2f0/4];
40 u32 pipe_0x6c00[0x030/4];
41 u32 pipe_0x7000[0x130/4];
42 u32 pipe_0x7400[0x0c0/4];
43 u32 pipe_0x7800[0x0c0/4];
[all …]
/linux/arch/mips/include/uapi/asm/
H A Dioctls.h15 #define TCGETA 0x5401
16 #define TCSETA 0x5402 /* Clashes with SNDCTL_TMR_START sound ioctl */
17 #define TCSETAW 0x5403
18 #define TCSETAF 0x5404
20 #define TCSBRK 0x5405
21 #define TCXONC 0x5406
22 #define TCFLSH 0x5407
24 #define TCGETS 0x540d
25 #define TCSETS 0x540e
26 #define TCSETSW 0x540f
[all …]
/linux/drivers/dma/ti/
H A Dk3-psil-j7200.c64 PSIL_PDMA_MCASP(0x4400),
65 PSIL_PDMA_MCASP(0x4401),
66 PSIL_PDMA_MCASP(0x4402),
68 PSIL_PDMA_XY_PKT(0x4600),
69 PSIL_PDMA_XY_PKT(0x4601),
70 PSIL_PDMA_XY_PKT(0x4602),
71 PSIL_PDMA_XY_PKT(0x4603),
72 PSIL_PDMA_XY_PKT(0x4604),
73 PSIL_PDMA_XY_PKT(0x4605),
74 PSIL_PDMA_XY_PKT(0x4606),
[all …]
H A Dk3-psil-j721s2.c71 PSIL_PDMA_MCASP(0x4400),
72 PSIL_PDMA_MCASP(0x4401),
73 PSIL_PDMA_MCASP(0x4402),
74 PSIL_PDMA_MCASP(0x4403),
75 PSIL_PDMA_MCASP(0x4404),
77 PSIL_PDMA_XY_PKT(0x4600),
78 PSIL_PDMA_XY_PKT(0x4601),
79 PSIL_PDMA_XY_PKT(0x4602),
80 PSIL_PDMA_XY_PKT(0x4603),
81 PSIL_PDMA_XY_PKT(0x4604),
[all …]
H A Dk3-psil-j784s4.c71 PSIL_PDMA_MCASP(0x4400),
72 PSIL_PDMA_MCASP(0x4401),
73 PSIL_PDMA_MCASP(0x4402),
74 PSIL_PDMA_MCASP(0x4403),
75 PSIL_PDMA_MCASP(0x4404),
77 PSIL_PDMA_XY_PKT(0x4600),
78 PSIL_PDMA_XY_PKT(0x4601),
79 PSIL_PDMA_XY_PKT(0x4602),
80 PSIL_PDMA_XY_PKT(0x4603),
81 PSIL_PDMA_XY_PKT(0x4604),
[all …]
H A Dk3-psil-j721e.c72 PSIL_SA2UL(0x4000, 0),
73 PSIL_SA2UL(0x4001, 0),
74 PSIL_SA2UL(0x4002, 0),
75 PSIL_SA2UL(0x4003, 0),
77 PSIL_ETHERNET(0x4100),
78 PSIL_ETHERNET(0x4101),
79 PSIL_ETHERNET(0x4102),
80 PSIL_ETHERNET(0x4103),
82 PSIL_ETHERNET(0x4200),
83 PSIL_ETHERNET(0x4201),
[all …]
/linux/sound/soc/codecs/
H A Drt711.h32 #define RT711_AUDIO_FUNCTION_GROUP 0x01
33 #define RT711_DAC_OUT2 0x03
34 #define RT711_ADC_IN1 0x09
35 #define RT711_ADC_IN2 0x08
36 #define RT711_DMIC1 0x12
37 #define RT711_DMIC2 0x13
38 #define RT711_MIC2 0x19
39 #define RT711_LINE1 0x1a
40 #define RT711_LINE2 0x1b
41 #define RT711_BEEP 0x1d
[all …]
H A Drt5645.c47 #define RT5645_DEVICE_ID 0x6308
48 #define RT5650_DEVICE_ID 0x6419
50 #define RT5645_PR_RANGE_BASE (0xff + 1)
51 #define RT5645_PR_SPACING 0x100
53 #define RT5645_PR_BASE (RT5645_PR_RANGE_BASE + (0 * RT5645_PR_SPACING))
63 .range_max = RT5645_PR_BASE + 0xf8,
65 .selector_mask = 0xff,
66 .selector_shift = 0x0,
68 .window_len = 0x1,
73 {RT5645_PR_BASE + 0x3d, 0x3600},
[all …]
/linux/drivers/cpufreq/
H A Dsun50i-cpufreq-nvmem.c22 #define NVMEM_MASK 0x7
25 #define SUN50I_A100_NVMEM_MASK 0xf
48 return 0; in sun50i_h6_efuse_xlate()
59 case 0b100: in sun50i_a100_efuse_xlate()
61 case 0b010: in sun50i_a100_efuse_xlate()
64 return 0; in sun50i_a100_efuse_xlate()
79 * returned speedbin index is 4 -> 0/2 -> 3 -> 1, from worst to best.
80 * 0 and 2 seem identical from the OPP tables' point of view.
85 u32 value = 0; in sun50i_h616_efuse_xlate()
87 switch (speedbin & 0xffff) { in sun50i_h616_efuse_xlate()
[all …]
/linux/drivers/net/wireless/ath/ath10k/
H A Dcoredump.c21 {0x800, 0x810},
22 {0x820, 0x82C},
23 {0x830, 0x8F4},
24 {0x90C, 0x91C},
25 {0xA14, 0xA18},
26 {0xA84, 0xA94},
27 {0xAA8, 0xAD4},
28 {0xADC, 0xB40},
29 {0x1000, 0x10A4},
30 {0x10BC, 0x111C},
[all …]
/linux/drivers/scsi/qla2xxx/
H A Dqla_dbg.c13 * | Module Init and Probe | 0x0199 | |
14 * | Mailbox commands | 0x1206 | 0x11a5-0x11ff |
15 * | Device Discovery | 0x2134 | 0x2112-0x2115 |
16 * | | | 0x2127-0x2128 |
17 * | Queue Command and IO tracing | 0x3074 | 0x300b |
18 * | | | 0x3027-0x3028 |
19 * | | | 0x303d-0x3041 |
20 * | | | 0x302e,0x3033 |
21 * | | | 0x3036,0x3038 |
22 * | | | 0x303a |
[all …]
/linux/drivers/video/fbdev/
H A Dgxt4500.c19 #define PCI_DEVICE_ID_IBM_GXT4500P 0x21c
20 #define PCI_DEVICE_ID_IBM_GXT6500P 0x21b
21 #define PCI_DEVICE_ID_IBM_GXT4000P 0x16e
22 #define PCI_DEVICE_ID_IBM_GXT6000P 0x170
27 #define CFG_ENDIAN0 0x40
30 #define STATUS 0x1000
31 #define CTRL_REG0 0x1004
32 #define CR0_HALT_DMA 0x4
33 #define CR0_RASTER_RESET 0x8
34 #define CR0_GEOM_RESET 0x10
[all …]
/linux/drivers/scsi/
H A Dsense_codes.h7 SENSE_CODE(0x0000, "No additional sense information")
8 SENSE_CODE(0x0001, "Filemark detected")
9 SENSE_CODE(0x0002, "End-of-partition/medium detected")
10 SENSE_CODE(0x0003, "Setmark detected")
11 SENSE_CODE(0x0004, "Beginning-of-partition/medium detected")
12 SENSE_CODE(0x0005, "End-of-data detected")
13 SENSE_CODE(0x0006, "I/O process terminated")
14 SENSE_CODE(0x0007, "Programmable early warning detected")
15 SENSE_CODE(0x0011, "Audio play operation in progress")
16 SENSE_CODE(0x0012, "Audio play operation paused")
[all …]
/linux/drivers/phy/marvell/
H A Dphy-mvebu-a3700-comphy.c33 #define COMPHY_LANE2_INDIR_ADDR 0x0
34 #define COMPHY_LANE2_INDIR_DATA 0x4
37 #define COMPHY_LANE2_REGS_BASE 0x200
43 #define COMPHY_LANE_REG_DIRECT(reg) (((reg) & 0x7FF) << 1)
46 #define COMPHY_POWER_PLL_CTRL 0x01
55 #define REF_FREF_SEL_MASK GENMASK(4, 0)
56 #define REF_FREF_SEL_SERDES_25MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x1)
57 #define REF_FREF_SEL_SERDES_40MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x3)
58 #define REF_FREF_SEL_SERDES_50MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x4)
59 #define REF_FREF_SEL_PCIE_USB3_25MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x2)
[all …]
/linux/drivers/net/ethernet/marvell/mvpp2/
H A Dmvpp2.h28 #define MVPP2_XDP_PASS 0
29 #define MVPP2_XDP_DROPPED BIT(0)
34 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
35 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
36 #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
37 #define MVPP2_RX_FIFO_INIT_REG 0x64
38 #define MVPP22_TX_FIFO_THRESH_REG(port) (0x8840 + 4 * (port))
39 #define MVPP22_TX_FIFO_SIZE_REG(port) (0x8860 + 4 * (port))
42 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
43 #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
[all …]
/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw88xxa.c42 (efuse->pa_type_5g & BIT(0)); in rtw8812a_read_amplifier_type()
63 BIT(1) | BIT(0)); in rtw8812a_read_amplifier_type()
72 BIT(1) | BIT(0)); in rtw8812a_read_amplifier_type()
85 if (map->rfe_option == 0xff) { in rtw8812a_read_rfe_type()
87 efuse->rfe_option = 0; in rtw8812a_read_rfe_type()
98 efuse->rfe_option = 0; in rtw8812a_read_rfe_type()
106 efuse->rfe_option = map->rfe_option & 0x3f; in rtw8812a_read_rfe_type()
110 * modify spec and notify all customer to revise the IC 0xca in rtw8812a_read_rfe_type()
117 efuse->rfe_option = 0; in rtw8812a_read_rfe_type()
128 u8 antenna = 0; in rtw88xxa_read_usb_type()
[all …]
/linux/drivers/net/ethernet/tehuti/
H A Dtehuti.c66 { PCI_VDEVICE(TEHUTI, 0x3009), },
67 { PCI_VDEVICE(TEHUTI, 0x3010), },
68 { PCI_VDEVICE(TEHUTI, 0x3014), },
69 { 0 }
100 u16 pci_link_status = 0; in print_hw_id()
101 u16 pci_ctrl = 0; in print_hw_id()
108 pr_info("srom 0x%x fpga %d build %u lane# %d max_pl 0x%x mrrs 0x%x\n", in print_hw_id()
109 readl(nic->regs + SROM_VER), readl(nic->regs + FPGA_VER) & 0xFFF, in print_hw_id()
117 pr_info("fw 0x%x\n", readl(nic->regs + FW_VER)); in print_fw_id()
123 BDX_NIC_NAME, (ndev->if_port == 0) ? 'A' : 'B'); in print_eth_id()
[all …]

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