Lines Matching +full:0 +full:x7400
34 u32 pipe_0x0000[0x040/4];
35 u32 pipe_0x0040[0x010/4];
36 u32 pipe_0x0200[0x0c0/4];
37 u32 pipe_0x4400[0x080/4];
38 u32 pipe_0x6400[0x3b0/4];
39 u32 pipe_0x6800[0x2f0/4];
40 u32 pipe_0x6c00[0x030/4];
41 u32 pipe_0x7000[0x130/4];
42 u32 pipe_0x7400[0x0c0/4];
43 u32 pipe_0x7800[0x0c0/4];
47 NV10_PGRAPH_CTX_SWITCH(0),
52 NV10_PGRAPH_CTX_CACHE(0, 0),
53 NV10_PGRAPH_CTX_CACHE(0, 1),
54 NV10_PGRAPH_CTX_CACHE(0, 2),
55 NV10_PGRAPH_CTX_CACHE(0, 3),
56 NV10_PGRAPH_CTX_CACHE(0, 4),
57 NV10_PGRAPH_CTX_CACHE(1, 0),
62 NV10_PGRAPH_CTX_CACHE(2, 0),
67 NV10_PGRAPH_CTX_CACHE(3, 0),
72 NV10_PGRAPH_CTX_CACHE(4, 0),
77 NV10_PGRAPH_CTX_CACHE(5, 0),
82 NV10_PGRAPH_CTX_CACHE(6, 0),
87 NV10_PGRAPH_CTX_CACHE(7, 0),
129 NV04_PGRAPH_PATT_COLORRAM, /* 64 values from 0x400900 to 0x4009fc */
130 0x00400904,
131 0x00400908,
132 0x0040090c,
133 0x00400910,
134 0x00400914,
135 0x00400918,
136 0x0040091c,
137 0x00400920,
138 0x00400924,
139 0x00400928,
140 0x0040092c,
141 0x00400930,
142 0x00400934,
143 0x00400938,
144 0x0040093c,
145 0x00400940,
146 0x00400944,
147 0x00400948,
148 0x0040094c,
149 0x00400950,
150 0x00400954,
151 0x00400958,
152 0x0040095c,
153 0x00400960,
154 0x00400964,
155 0x00400968,
156 0x0040096c,
157 0x00400970,
158 0x00400974,
159 0x00400978,
160 0x0040097c,
161 0x00400980,
162 0x00400984,
163 0x00400988,
164 0x0040098c,
165 0x00400990,
166 0x00400994,
167 0x00400998,
168 0x0040099c,
169 0x004009a0,
170 0x004009a4,
171 0x004009a8,
172 0x004009ac,
173 0x004009b0,
174 0x004009b4,
175 0x004009b8,
176 0x004009bc,
177 0x004009c0,
178 0x004009c4,
179 0x004009c8,
180 0x004009cc,
181 0x004009d0,
182 0x004009d4,
183 0x004009d8,
184 0x004009dc,
185 0x004009e0,
186 0x004009e4,
187 0x004009e8,
188 0x004009ec,
189 0x004009f0,
190 0x004009f4,
191 0x004009f8,
192 0x004009fc,
193 NV04_PGRAPH_PATTERN, /* 2 values from 0x400808 to 0x40080c */
194 0x0040080c,
201 0x00400e70,
202 0x00400e74,
203 0x00400e78,
204 0x00400e7c,
205 0x00400e80,
206 0x00400e84,
207 0x00400e88,
208 0x00400e8c,
209 0x00400ea0,
210 0x00400ea4,
211 0x00400ea8,
212 0x00400e90,
213 0x00400e94,
214 0x00400e98,
215 0x00400e9c,
216 NV10_PGRAPH_WINDOWCLIP_HORIZONTAL, /* 8 values from 0x400f00-0x400f1c */
217 NV10_PGRAPH_WINDOWCLIP_VERTICAL, /* 8 values from 0x400f20-0x400f3c */
218 0x00400f04,
219 0x00400f24,
220 0x00400f08,
221 0x00400f28,
222 0x00400f0c,
223 0x00400f2c,
224 0x00400f10,
225 0x00400f30,
226 0x00400f14,
227 0x00400f34,
228 0x00400f18,
229 0x00400f38,
230 0x00400f1c,
231 0x00400f3c,
238 NV03_PGRAPH_ABS_X_RAM, /* 32 values from 0x400400 to 0x40047c */
239 NV03_PGRAPH_ABS_Y_RAM, /* 32 values from 0x400480 to 0x4004fc */
240 0x00400404,
241 0x00400484,
242 0x00400408,
243 0x00400488,
244 0x0040040c,
245 0x0040048c,
246 0x00400410,
247 0x00400490,
248 0x00400414,
249 0x00400494,
250 0x00400418,
251 0x00400498,
252 0x0040041c,
253 0x0040049c,
254 0x00400420,
255 0x004004a0,
256 0x00400424,
257 0x004004a4,
258 0x00400428,
259 0x004004a8,
260 0x0040042c,
261 0x004004ac,
262 0x00400430,
263 0x004004b0,
264 0x00400434,
265 0x004004b4,
266 0x00400438,
267 0x004004b8,
268 0x0040043c,
269 0x004004bc,
270 0x00400440,
271 0x004004c0,
272 0x00400444,
273 0x004004c4,
274 0x00400448,
275 0x004004c8,
276 0x0040044c,
277 0x004004cc,
278 0x00400450,
279 0x004004d0,
280 0x00400454,
281 0x004004d4,
282 0x00400458,
283 0x004004d8,
284 0x0040045c,
285 0x004004dc,
286 0x00400460,
287 0x004004e0,
288 0x00400464,
289 0x004004e4,
290 0x00400468,
291 0x004004e8,
292 0x0040046c,
293 0x004004ec,
294 0x00400470,
295 0x004004f0,
296 0x00400474,
297 0x004004f4,
298 0x00400478,
299 0x004004f8,
300 0x0040047c,
301 0x004004fc,
306 0x00400550,
307 0x00400558,
308 0x00400554,
309 0x0040055c,
336 0x00400e00,
337 0x00400e04,
338 0x00400e08,
339 0x00400e0c,
340 0x00400e10,
341 0x00400e14,
342 0x00400e18,
343 0x00400e1c,
344 0x00400e20,
345 0x00400e24,
346 0x00400e28,
347 0x00400e2c,
348 0x00400e30,
349 0x00400e34,
350 0x00400e38,
351 0x00400e3c,
370 0x004006b0,
371 0x00400eac,
372 0x00400eb0,
373 0x00400eb4,
374 0x00400eb8,
375 0x00400ebc,
376 0x00400ec0,
377 0x00400ec4,
378 0x00400ec8,
379 0x00400ecc,
380 0x00400ed0,
381 0x00400ed4,
382 0x00400ed8,
383 0x00400edc,
384 0x00400ee0,
385 0x00400a00,
386 0x00400a04,
418 for (__i = 0; __i < ARRAY_SIZE(state); __i++) \
420 } while (0)
426 for (__i = 0; __i < ARRAY_SIZE(state); __i++) \
428 } while (0)
440 chan->lma_window[(mthd - 0x1638) / 4] = data; in nv17_gr_mthd_lma_window()
442 if (mthd != 0x1644) in nv17_gr_mthd_lma_window()
447 PIPE_SAVE(device, pipe_0x0040, 0x0040); in nv17_gr_mthd_lma_window()
448 PIPE_SAVE(device, pipe->pipe_0x0200, 0x0200); in nv17_gr_mthd_lma_window()
450 PIPE_RESTORE(device, chan->lma_window, 0x6790); in nv17_gr_mthd_lma_window()
457 PIPE_SAVE(device, pipe->pipe_0x4400, 0x4400); in nv17_gr_mthd_lma_window()
458 PIPE_SAVE(device, pipe_0x64c0, 0x64c0); in nv17_gr_mthd_lma_window()
459 PIPE_SAVE(device, pipe_0x6ab0, 0x6ab0); in nv17_gr_mthd_lma_window()
460 PIPE_SAVE(device, pipe_0x6a80, 0x6a80); in nv17_gr_mthd_lma_window()
464 nvkm_wr32(device, NV10_PGRAPH_XFMODE0, 0x10000000); in nv17_gr_mthd_lma_window()
465 nvkm_wr32(device, NV10_PGRAPH_XFMODE1, 0x00000000); in nv17_gr_mthd_lma_window()
466 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0); in nv17_gr_mthd_lma_window()
467 for (i = 0; i < 4; i++) in nv17_gr_mthd_lma_window()
468 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x3f800000); in nv17_gr_mthd_lma_window()
469 for (i = 0; i < 4; i++) in nv17_gr_mthd_lma_window()
470 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000000); in nv17_gr_mthd_lma_window()
472 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0); in nv17_gr_mthd_lma_window()
473 for (i = 0; i < 3; i++) in nv17_gr_mthd_lma_window()
474 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x3f800000); in nv17_gr_mthd_lma_window()
476 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80); in nv17_gr_mthd_lma_window()
477 for (i = 0; i < 3; i++) in nv17_gr_mthd_lma_window()
478 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000000); in nv17_gr_mthd_lma_window()
480 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040); in nv17_gr_mthd_lma_window()
481 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000008); in nv17_gr_mthd_lma_window()
483 PIPE_RESTORE(device, pipe->pipe_0x0200, 0x0200); in nv17_gr_mthd_lma_window()
487 PIPE_RESTORE(device, pipe_0x0040, 0x0040); in nv17_gr_mthd_lma_window()
492 PIPE_RESTORE(device, pipe_0x64c0, 0x64c0); in nv17_gr_mthd_lma_window()
493 PIPE_RESTORE(device, pipe_0x6ab0, 0x6ab0); in nv17_gr_mthd_lma_window()
494 PIPE_RESTORE(device, pipe_0x6a80, 0x6a80); in nv17_gr_mthd_lma_window()
495 PIPE_RESTORE(device, pipe->pipe_0x4400, 0x4400); in nv17_gr_mthd_lma_window()
497 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x000000c0); in nv17_gr_mthd_lma_window()
498 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000000); in nv17_gr_mthd_lma_window()
511 nvkm_mask(device, NV10_PGRAPH_DEBUG_4, 0x00000100, 0x00000100); in nv17_gr_mthd_lma_enable()
512 nvkm_mask(device, 0x4006b0, 0x08000000, 0x08000000); in nv17_gr_mthd_lma_enable()
520 case 0x1638 ... 0x1644: in nv17_gr_mthd_celcius()
522 case 0x1658: func = nv17_gr_mthd_lma_enable; break; in nv17_gr_mthd_celcius()
535 case 0x99: func = nv17_gr_mthd_celcius; break; in nv10_gr_mthd()
551 if (nvkm_rd32(device, 0x400144) & 0x00010000) { in nv10_gr_channel()
552 int chid = nvkm_rd32(device, 0x400148) >> 24; in nv10_gr_channel()
566 PIPE_SAVE(gr, pipe->pipe_0x4400, 0x4400); in nv10_gr_save_pipe()
567 PIPE_SAVE(gr, pipe->pipe_0x0200, 0x0200); in nv10_gr_save_pipe()
568 PIPE_SAVE(gr, pipe->pipe_0x6400, 0x6400); in nv10_gr_save_pipe()
569 PIPE_SAVE(gr, pipe->pipe_0x6800, 0x6800); in nv10_gr_save_pipe()
570 PIPE_SAVE(gr, pipe->pipe_0x6c00, 0x6c00); in nv10_gr_save_pipe()
571 PIPE_SAVE(gr, pipe->pipe_0x7000, 0x7000); in nv10_gr_save_pipe()
572 PIPE_SAVE(gr, pipe->pipe_0x7400, 0x7400); in nv10_gr_save_pipe()
573 PIPE_SAVE(gr, pipe->pipe_0x7800, 0x7800); in nv10_gr_save_pipe()
574 PIPE_SAVE(gr, pipe->pipe_0x0040, 0x0040); in nv10_gr_save_pipe()
575 PIPE_SAVE(gr, pipe->pipe_0x0000, 0x0000); in nv10_gr_save_pipe()
591 nvkm_wr32(device, NV10_PGRAPH_XFMODE0, 0x10000000); in nv10_gr_load_pipe()
592 nvkm_wr32(device, NV10_PGRAPH_XFMODE1, 0x00000000); in nv10_gr_load_pipe()
593 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0); in nv10_gr_load_pipe()
594 for (i = 0; i < 4; i++) in nv10_gr_load_pipe()
595 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x3f800000); in nv10_gr_load_pipe()
596 for (i = 0; i < 4; i++) in nv10_gr_load_pipe()
597 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000000); in nv10_gr_load_pipe()
599 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0); in nv10_gr_load_pipe()
600 for (i = 0; i < 3; i++) in nv10_gr_load_pipe()
601 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x3f800000); in nv10_gr_load_pipe()
603 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80); in nv10_gr_load_pipe()
604 for (i = 0; i < 3; i++) in nv10_gr_load_pipe()
605 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000000); in nv10_gr_load_pipe()
607 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040); in nv10_gr_load_pipe()
608 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000008); in nv10_gr_load_pipe()
611 PIPE_RESTORE(gr, pipe->pipe_0x0200, 0x0200); in nv10_gr_load_pipe()
617 PIPE_RESTORE(gr, pipe->pipe_0x6400, 0x6400); in nv10_gr_load_pipe()
618 PIPE_RESTORE(gr, pipe->pipe_0x6800, 0x6800); in nv10_gr_load_pipe()
619 PIPE_RESTORE(gr, pipe->pipe_0x6c00, 0x6c00); in nv10_gr_load_pipe()
620 PIPE_RESTORE(gr, pipe->pipe_0x7000, 0x7000); in nv10_gr_load_pipe()
621 PIPE_RESTORE(gr, pipe->pipe_0x7400, 0x7400); in nv10_gr_load_pipe()
622 PIPE_RESTORE(gr, pipe->pipe_0x7800, 0x7800); in nv10_gr_load_pipe()
623 PIPE_RESTORE(gr, pipe->pipe_0x4400, 0x4400); in nv10_gr_load_pipe()
624 PIPE_RESTORE(gr, pipe->pipe_0x0000, 0x0000); in nv10_gr_load_pipe()
625 PIPE_RESTORE(gr, pipe->pipe_0x0040, 0x0040); in nv10_gr_load_pipe()
640 } while (0) in nv10_gr_create_pipe()
646 nvkm_error(subdev, "incomplete pipe init for 0x%x : %p/%p\n", \ in nv10_gr_create_pipe()
648 } while (0) in nv10_gr_create_pipe()
651 PIPE_INIT(0x0200); in nv10_gr_create_pipe()
652 for (i = 0; i < 48; i++) in nv10_gr_create_pipe()
653 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
654 PIPE_INIT_END(0x0200); in nv10_gr_create_pipe()
656 PIPE_INIT(0x6400); in nv10_gr_create_pipe()
657 for (i = 0; i < 211; i++) in nv10_gr_create_pipe()
658 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
659 NV_WRITE_PIPE_INIT(0x3f800000); in nv10_gr_create_pipe()
660 NV_WRITE_PIPE_INIT(0x40000000); in nv10_gr_create_pipe()
661 NV_WRITE_PIPE_INIT(0x40000000); in nv10_gr_create_pipe()
662 NV_WRITE_PIPE_INIT(0x40000000); in nv10_gr_create_pipe()
663 NV_WRITE_PIPE_INIT(0x40000000); in nv10_gr_create_pipe()
664 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
665 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
666 NV_WRITE_PIPE_INIT(0x3f800000); in nv10_gr_create_pipe()
667 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
668 NV_WRITE_PIPE_INIT(0x3f000000); in nv10_gr_create_pipe()
669 NV_WRITE_PIPE_INIT(0x3f000000); in nv10_gr_create_pipe()
670 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
671 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
672 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
673 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
674 NV_WRITE_PIPE_INIT(0x3f800000); in nv10_gr_create_pipe()
675 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
676 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
677 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
678 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
679 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
680 NV_WRITE_PIPE_INIT(0x3f800000); in nv10_gr_create_pipe()
681 NV_WRITE_PIPE_INIT(0x3f800000); in nv10_gr_create_pipe()
682 NV_WRITE_PIPE_INIT(0x3f800000); in nv10_gr_create_pipe()
683 NV_WRITE_PIPE_INIT(0x3f800000); in nv10_gr_create_pipe()
684 PIPE_INIT_END(0x6400); in nv10_gr_create_pipe()
686 PIPE_INIT(0x6800); in nv10_gr_create_pipe()
687 for (i = 0; i < 162; i++) in nv10_gr_create_pipe()
688 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
689 NV_WRITE_PIPE_INIT(0x3f800000); in nv10_gr_create_pipe()
690 for (i = 0; i < 25; i++) in nv10_gr_create_pipe()
691 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
692 PIPE_INIT_END(0x6800); in nv10_gr_create_pipe()
694 PIPE_INIT(0x6c00); in nv10_gr_create_pipe()
695 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
696 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
697 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
698 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
699 NV_WRITE_PIPE_INIT(0xbf800000); in nv10_gr_create_pipe()
700 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
701 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
702 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
703 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
704 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
705 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
706 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
707 PIPE_INIT_END(0x6c00); in nv10_gr_create_pipe()
709 PIPE_INIT(0x7000); in nv10_gr_create_pipe()
710 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
711 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
712 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
713 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
714 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
715 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
716 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
717 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
718 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
719 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
720 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
721 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
722 NV_WRITE_PIPE_INIT(0x7149f2ca); in nv10_gr_create_pipe()
723 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
724 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
725 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
726 NV_WRITE_PIPE_INIT(0x7149f2ca); in nv10_gr_create_pipe()
727 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
728 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
729 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
730 NV_WRITE_PIPE_INIT(0x7149f2ca); in nv10_gr_create_pipe()
731 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
732 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
733 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
734 NV_WRITE_PIPE_INIT(0x7149f2ca); in nv10_gr_create_pipe()
735 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
736 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
737 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
738 NV_WRITE_PIPE_INIT(0x7149f2ca); in nv10_gr_create_pipe()
739 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
740 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
741 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
742 NV_WRITE_PIPE_INIT(0x7149f2ca); in nv10_gr_create_pipe()
743 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
744 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
745 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
746 NV_WRITE_PIPE_INIT(0x7149f2ca); in nv10_gr_create_pipe()
747 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
748 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
749 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
750 NV_WRITE_PIPE_INIT(0x7149f2ca); in nv10_gr_create_pipe()
751 for (i = 0; i < 35; i++) in nv10_gr_create_pipe()
752 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
753 PIPE_INIT_END(0x7000); in nv10_gr_create_pipe()
755 PIPE_INIT(0x7400); in nv10_gr_create_pipe()
756 for (i = 0; i < 48; i++) in nv10_gr_create_pipe()
757 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
758 PIPE_INIT_END(0x7400); in nv10_gr_create_pipe()
760 PIPE_INIT(0x7800); in nv10_gr_create_pipe()
761 for (i = 0; i < 48; i++) in nv10_gr_create_pipe()
762 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
763 PIPE_INIT_END(0x7800); in nv10_gr_create_pipe()
765 PIPE_INIT(0x4400); in nv10_gr_create_pipe()
766 for (i = 0; i < 32; i++) in nv10_gr_create_pipe()
767 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
768 PIPE_INIT_END(0x4400); in nv10_gr_create_pipe()
770 PIPE_INIT(0x0000); in nv10_gr_create_pipe()
771 for (i = 0; i < 16; i++) in nv10_gr_create_pipe()
772 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
773 PIPE_INIT_END(0x0000); in nv10_gr_create_pipe()
775 PIPE_INIT(0x0040); in nv10_gr_create_pipe()
776 for (i = 0; i < 4; i++) in nv10_gr_create_pipe()
777 NV_WRITE_PIPE_INIT(0x00000000); in nv10_gr_create_pipe()
778 PIPE_INIT_END(0x0040); in nv10_gr_create_pipe()
790 for (i = 0; i < ARRAY_SIZE(nv10_gr_ctx_regs); i++) { in nv10_gr_ctx_regs_find_offset()
803 for (i = 0; i < ARRAY_SIZE(nv17_gr_ctx_regs); i++) { in nv17_gr_ctx_regs_find_offset()
816 u32 st2, st2_dl, st2_dh, fifo_ptr, fifo[0x60/4]; in nv10_gr_load_dma_vtxbuf()
820 /* NV10TCL_DMA_VTXBUF (method 0x18c) modifies hidden state in nv10_gr_load_dma_vtxbuf()
826 for (i = 0; i < 8; i++) { in nv10_gr_load_dma_vtxbuf()
827 int class = nvkm_rd32(device, NV10_PGRAPH_CTX_CACHE(i, 0)) & 0xfff; in nv10_gr_load_dma_vtxbuf()
829 if (class == 0x56 || class == 0x96 || class == 0x99) { in nv10_gr_load_dma_vtxbuf()
835 if (subchan < 0 || !inst) in nv10_gr_load_dma_vtxbuf()
840 for (i = 0; i < 5; i++) in nv10_gr_load_dma_vtxbuf()
849 for (i = 0; i < ARRAY_SIZE(fifo); i++) in nv10_gr_load_dma_vtxbuf()
850 fifo[i] = nvkm_rd32(device, 0x4007a0 + 4 * i); in nv10_gr_load_dma_vtxbuf()
853 for (i = 0; i < 5; i++) in nv10_gr_load_dma_vtxbuf()
856 nvkm_mask(device, NV10_PGRAPH_CTX_USER, 0xe000, subchan << 13); in nv10_gr_load_dma_vtxbuf()
859 nvkm_wr32(device, NV10_PGRAPH_FFINTFC_FIFO_PTR, 0); in nv10_gr_load_dma_vtxbuf()
861 0x2c000000 | chid << 20 | subchan << 16 | 0x18c); in nv10_gr_load_dma_vtxbuf()
863 nvkm_mask(device, NV10_PGRAPH_CTX_CONTROL, 0, 0x10000); in nv10_gr_load_dma_vtxbuf()
864 nvkm_mask(device, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001); in nv10_gr_load_dma_vtxbuf()
865 nvkm_mask(device, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000); in nv10_gr_load_dma_vtxbuf()
868 for (i = 0; i < ARRAY_SIZE(fifo); i++) in nv10_gr_load_dma_vtxbuf()
869 nvkm_wr32(device, 0x4007a0 + 4 * i, fifo[i]); in nv10_gr_load_dma_vtxbuf()
877 for (i = 0; i < 5; i++) in nv10_gr_load_dma_vtxbuf()
890 for (i = 0; i < ARRAY_SIZE(nv10_gr_ctx_regs); i++) in nv10_gr_load_context()
893 if (device->card_type >= NV_11 && device->chipset >= 0x17) { in nv10_gr_load_context()
894 for (i = 0; i < ARRAY_SIZE(nv17_gr_ctx_regs); i++) in nv10_gr_load_context()
900 inst = nvkm_rd32(device, NV10_PGRAPH_GLOBALSTATE1) & 0xffff; in nv10_gr_load_context()
903 nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10010100); in nv10_gr_load_context()
904 nvkm_mask(device, NV10_PGRAPH_CTX_USER, 0xff000000, chid << 24); in nv10_gr_load_context()
905 nvkm_mask(device, NV10_PGRAPH_FFINTFC_ST2, 0x30000000, 0x00000000); in nv10_gr_load_context()
906 return 0; in nv10_gr_load_context()
916 for (i = 0; i < ARRAY_SIZE(nv10_gr_ctx_regs); i++) in nv10_gr_unload_context()
919 if (device->card_type >= NV_11 && device->chipset >= 0x17) { in nv10_gr_unload_context()
920 for (i = 0; i < ARRAY_SIZE(nv17_gr_ctx_regs); i++) in nv10_gr_unload_context()
926 nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10000000); in nv10_gr_unload_context()
927 nvkm_mask(device, NV10_PGRAPH_CTX_USER, 0xff000000, 0x1f000000); in nv10_gr_unload_context()
928 return 0; in nv10_gr_unload_context()
947 chid = (nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f; in nv10_gr_context_switch()
962 nvkm_mask(device, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000); in nv10_gr_chan_fini()
965 nvkm_mask(device, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001); in nv10_gr_chan_fini()
967 return 0; in nv10_gr_chan_fini()
991 if (offset > 0) \
993 } while (0)
997 if (offset > 0) \
999 } while (0)
1017 NV_WRITE_CTX(0x00400e88, 0x08000000); in nv10_gr_chan_new()
1018 NV_WRITE_CTX(0x00400e9c, 0x4b7fffff); in nv10_gr_chan_new()
1019 NV_WRITE_CTX(NV03_PGRAPH_XY_LOGIC_MISC0, 0x0001ffff); in nv10_gr_chan_new()
1020 NV_WRITE_CTX(0x00400e10, 0x00001000); in nv10_gr_chan_new()
1021 NV_WRITE_CTX(0x00400e14, 0x00001000); in nv10_gr_chan_new()
1022 NV_WRITE_CTX(0x00400e30, 0x00080008); in nv10_gr_chan_new()
1023 NV_WRITE_CTX(0x00400e34, 0x00080008); in nv10_gr_chan_new()
1024 if (device->card_type >= NV_11 && device->chipset >= 0x17) { in nv10_gr_chan_new()
1028 NV17_WRITE_CTX(0x004006b0, nvkm_rd32(device, 0x004006b0)); in nv10_gr_chan_new()
1029 NV17_WRITE_CTX(0x00400eac, 0x0fff0000); in nv10_gr_chan_new()
1030 NV17_WRITE_CTX(0x00400eb0, 0x0fff0000); in nv10_gr_chan_new()
1031 NV17_WRITE_CTX(0x00400ec0, 0x00000080); in nv10_gr_chan_new()
1032 NV17_WRITE_CTX(0x00400ed0, 0x00000080); in nv10_gr_chan_new()
1041 return 0; in nv10_gr_chan_new()
1090 u32 chid = (addr & 0x01f00000) >> 20; in nv10_gr_intr()
1091 u32 subc = (addr & 0x00070000) >> 16; in nv10_gr_intr()
1092 u32 mthd = (addr & 0x00001ffc); in nv10_gr_intr()
1094 u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xfff; in nv10_gr_intr()
1118 nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001); in nv10_gr_intr()
1141 nvkm_wr32(device, NV03_PGRAPH_INTR , 0xFFFFFFFF); in nv10_gr_init()
1142 nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); in nv10_gr_init()
1144 nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); in nv10_gr_init()
1145 nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000); in nv10_gr_init()
1146 nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x00118700); in nv10_gr_init()
1147 /* nvkm_wr32(device, NV04_PGRAPH_DEBUG_2, 0x24E00810); */ /* 0x25f92ad9 */ in nv10_gr_init()
1148 nvkm_wr32(device, NV04_PGRAPH_DEBUG_2, 0x25f92ad9); in nv10_gr_init()
1149 nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0x55DE0830 | (1 << 29) | (1 << 31)); in nv10_gr_init()
1151 if (device->card_type >= NV_11 && device->chipset >= 0x17) { in nv10_gr_init()
1152 nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x1f000000); in nv10_gr_init()
1153 nvkm_wr32(device, 0x400a10, 0x03ff3fb6); in nv10_gr_init()
1154 nvkm_wr32(device, 0x400838, 0x002f8684); in nv10_gr_init()
1155 nvkm_wr32(device, 0x40083c, 0x00115f3f); in nv10_gr_init()
1156 nvkm_wr32(device, 0x4006b0, 0x40000020); in nv10_gr_init()
1158 nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00000000); in nv10_gr_init()
1161 nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(0), 0x00000000); in nv10_gr_init()
1162 nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(1), 0x00000000); in nv10_gr_init()
1163 nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(2), 0x00000000); in nv10_gr_init()
1164 nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(3), 0x00000000); in nv10_gr_init()
1165 nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(4), 0x00000000); in nv10_gr_init()
1166 nvkm_wr32(device, NV10_PGRAPH_STATE, 0xFFFFFFFF); in nv10_gr_init()
1168 nvkm_mask(device, NV10_PGRAPH_CTX_USER, 0xff000000, 0x1f000000); in nv10_gr_init()
1169 nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10000100); in nv10_gr_init()
1170 nvkm_wr32(device, NV10_PGRAPH_FFINTFC_ST2, 0x08000000); in nv10_gr_init()
1171 return 0; in nv10_gr_init()
1195 { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */
1196 { -1, -1, 0x0019, &nv04_gr_object }, /* clip */
1197 { -1, -1, 0x0030, &nv04_gr_object }, /* null */
1198 { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */
1199 { -1, -1, 0x0043, &nv04_gr_object }, /* rop */
1200 { -1, -1, 0x0044, &nv04_gr_object }, /* pattern */
1201 { -1, -1, 0x004a, &nv04_gr_object }, /* gdi */
1202 { -1, -1, 0x0052, &nv04_gr_object }, /* swzsurf */
1203 { -1, -1, 0x005f, &nv04_gr_object }, /* blit */
1204 { -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */
1205 { -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */
1206 { -1, -1, 0x0089, &nv04_gr_object }, /* sifm */
1207 { -1, -1, 0x008a, &nv04_gr_object }, /* ifc */
1208 { -1, -1, 0x009f, &nv04_gr_object }, /* blit */
1209 { -1, -1, 0x0093, &nv04_gr_object }, /* surf3d */
1210 { -1, -1, 0x0094, &nv04_gr_object }, /* ttri */
1211 { -1, -1, 0x0095, &nv04_gr_object }, /* mtri */
1212 { -1, -1, 0x0056, &nv04_gr_object }, /* celcius */