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/freebsd/sys/contrib/device-tree/Bindings/rtc/
H A Drtc-meson.txt27 reg = <0x740 0x14>;
H A Damlogic,meson6-rtc.yaml52 reg = <0x740 0x14>;
60 mac@0 {
61 reg = <0 6>;
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Damlogic,g12a-toacodec.yaml53 reg = <0x740 0x4>;
/freebsd/sys/dev/qlxge/
H A Dqls_dump.h37 #define Q81_MPID_COOKIE 0x5555aaaa
61 Q81_MPI_CORE_REGS_ADDR = 0x00030000,
64 Q81_TEST_REGS_ADDR = 0x00001000,
66 Q81_RMII_REGS_ADDR = 0x00001040,
68 Q81_FCMAC1_REGS_ADDR = 0x00001080,
69 Q81_FCMAC2_REGS_ADDR = 0x000010c0,
71 Q81_FC1_MBX_REGS_ADDR = 0x00001100,
72 Q81_FC2_MBX_REGS_ADDR = 0x00001240,
74 Q81_IDE_REGS_ADDR = 0x00001140,
76 Q81_NIC1_MBX_REGS_ADDR = 0x00001180,
[all …]
/freebsd/sys/dev/sound/pci/
H A Dcs4281.h32 #define CS4281_PCI_ID 0x60051013
39 #define CS4281PCI_HISR 0x000
40 # define CS4281PCI_HISR_DMAI 0x00040000
41 # define CS4281PCI_HISR_DMA(x) (0x0100 << (x))
43 #define CS4281PCI_HICR 0x008
44 # define CS4281PCI_HICR_EOI 0x00000003
46 #define CS4281PCI_HIMR 0x00c
47 # define CS4281PCI_HIMR_DMAI 0x00040000
48 # define CS4281PCI_HIMR_DMA(x) (0x0100 << (x))
50 #define CS4281PCI_IIER 0x010
[all …]
/freebsd/usr.sbin/fwget/pci/
H A Dpci_video_amd33 0x678*|0x679*)
36 0x680*|0x681*)
39 0x660*|0x661*|0x662*|0x663*)
42 0x682*|0x683*)
45 0x666*)
48 0x13*)
51 0x664*|0x665*)
54 0x67a*|0x67b*)
57 0x983*)
60 0x985*)
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6q-pinfunc.h13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
15 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
16 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
17 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
18 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
21 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
22 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
[all …]
H A Dimx6dl-pinfunc.h13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
H A Dimx51-pinfunc.h13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
[all …]
H A Dimx50-pinfunc.h13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
H A Dimx35-pinfunc.h13 #define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0
14 #define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0
15 #define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0
16 #define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0
17 #define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0
18 #define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0
19 #define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0
20 #define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0
21 #define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0
22 #define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0
[all …]
H A Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
/freebsd/sys/contrib/device-tree/src/arm/amlogic/
H A Dmeson.dtsi28 reg = <0xc1100000 0x200000>;
31 ranges = <0x0 0xc1100000 0x200000>;
37 reg = <0x4000 0x400>;
44 reg = <0x5400 0x2ac>;
53 reg = <0x7c00 0x200>;
58 reg = <0x8100 0x8>;
63 reg = <0x84c0 0x18>;
71 reg = <0x84dc 0x18>;
78 reg = <0x8500 0x20>;
81 #size-cells = <0>;
[all …]
/freebsd/sys/dev/thunderbolt/
H A Dtbcfg_reg.h40 #define TB_CFG_ADDR_SHIFT 0
41 #define TB_CFG_ADDR_MASK GENMASK(12,0)
46 #define TB_CFG_CS_PATH (0x00 << 25)
47 #define TB_CFG_CS_ADAPTER (0x01 << 25)
48 #define TB_CFG_CS_ROUTER (0x02 << 25)
49 #define TB_CFG_CS_COUNTERS (0x03 << 25)
59 uint32_t data[0]; /* Up to 60 dwords */
67 uint32_t data[0]; /* Up to 60 dwords */
82 #define TB_CFG_EVENT_MASK GENMASK(7,0)
84 #define TB_CFG_ERR_CONN 0x00
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/amlogic/
H A Dmeson-g12.dtsi14 tdmif_a: audio-controller-0 {
16 #sound-dai-cells = <0>;
27 #sound-dai-cells = <0>;
38 #sound-dai-cells = <0>;
52 reg = <0x0 0x40000 0x0 0x34>;
53 #sound-dai-cells = <0>;
65 reg = <0x0 0x42000 0x0 0x2000>;
68 ranges = <0x0 0x0 0x0 0x42000 0x0 0x2000>;
70 clkc_audio: clock-controller@0 {
73 reg = <0x0 0x0 0x0 0xb4>;
[all …]
H A Dmeson-sm1.dtsi16 tdmif_a: audio-controller-0 {
18 #sound-dai-cells = <0>;
29 #sound-dai-cells = <0>;
40 #sound-dai-cells = <0>;
50 #address-cells = <0x2>;
51 #size-cells = <0x0>;
53 cpu0: cpu@0 {
56 reg = <0x0 0x0>;
65 reg = <0x0 0x1>;
74 reg = <0x0 0x2>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Dqcom,dwc3.yaml143 "^usb@[0-9a-f]+$":
570 reg = <0 0x0a6f8800 0 0x400>;
604 reg = <0 0x0a600000 0 0xcd00>;
606 iommus = <&apps_smmu 0x740 0>;
/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_car.h39 #define RST_SOURCE 0x000
40 #define RST_DEVICES_L 0x004
41 #define RST_DEVICES_H 0x008
42 #define RST_DEVICES_U 0x00C
43 #define CLK_OUT_ENB_L 0x010
44 #define CLK_OUT_ENB_H 0x014
45 #define CLK_OUT_ENB_U 0x018
46 #define SUPER_CCLK_DIVIDER 0x024
47 #define SCLK_BURST_POLICY 0x028
48 #define SUPER_SCLK_DIVIDER 0x02c
[all …]
/freebsd/sys/arm/arm/
H A Dpl310.c73 } while(0);
77 } while(0);
174 if (setup != 0) { in pl310_set_ram_latency()
179 if (read != 0) { in pl310_set_ram_latency()
184 if (write != 0) { in pl310_set_ram_latency()
245 pl310_write4(pl310_softc, 0x740, 0xffffffff); in pl310_cache_sync()
248 pl310_write4(pl310_softc, PL310_CACHE_SYNC, 0xffffffff); in pl310_cache_sync()
263 for (i = 0; i < g_ways_assoc; i++) { in pl310_wbinv_all()
264 for (j = 0; j < g_way_size / g_l2cache_line_size; j++) { in pl310_wbinv_all()
282 platform_pl310_write_debug(pl310_softc, 0); in pl310_wbinv_all()
[all …]
/freebsd/crypto/heimdal/lib/wind/
H A Dcombining_table.c9 {0x300, 230}, /* Mn */
10 {0x301, 230}, /* Mn */
11 {0x302, 230}, /* Mn */
12 {0x303, 230}, /* Mn */
13 {0x304, 230}, /* Mn */
14 {0x305, 230}, /* Mn */
15 {0x306, 230}, /* Mn */
16 {0x307, 230}, /* Mn */
17 {0x308, 230}, /* Mn */
18 {0x309, 230}, /* Mn */
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSystemOperands.td3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
30 // Privilege Access: Read and Write = 0, 1, 2; Read-Only = 3.
31 // Privilege Mode: User = 0, System = 1 or Machine = 3.
37 // bits<6> Number = op{5 - 0};
39 bit isRV32Only = 0;
78 def SysRegFFLAGS : SysReg<"fflags", 0x001>;
79 def SysRegFRM : SysReg<"frm", 0x002>;
80 def SysRegFCSR : SysReg<"fcsr", 0x003>;
85 def CYCLE : SysReg<"cycle", 0xC00>;
86 def TIME : SysReg<"time", 0xC01>;
[all …]
/freebsd/sys/dev/clk/allwinner/
H A Dccu_d1.c56 CCU_RESET(RST_MBUS, 0x540, 30)
57 CCU_RESET(RST_BUS_DE, 0x60C, 16)
58 CCU_RESET(RST_BUS_DI, 0x62C, 16)
59 CCU_RESET(RST_BUS_G2D, 0x63C, 16)
60 CCU_RESET(RST_BUS_CE, 0x68C, 16)
61 CCU_RESET(RST_BUS_VE, 0x69C, 16)
62 CCU_RESET(RST_BUS_DMA, 0x70C, 16)
63 CCU_RESET(RST_BUS_MSGBOX0, 0x71C, 16)
64 CCU_RESET(RST_BUS_MSGBOX1, 0x71C, 17)
65 CCU_RESET(RST_BUS_MSGBOX2, 0x71C, 18)
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsdm670.dtsi33 #size-cells = <0>;
35 CPU0: cpu@0 {
38 reg = <0x0 0x0>;
42 qcom,freq-domain = <&cpufreq_hw 0>;
65 reg = <0x0 0x100>;
69 qcom,freq-domain = <&cpufreq_hw 0>;
87 reg = <0x0 0x200>;
91 qcom,freq-domain = <&cpufreq_hw 0>;
109 reg = <0x0 0x300>;
113 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
/freebsd/sys/contrib/dev/rtw89/
H A Drtw8852a.c15 #define RTW8852A_FW_FORMAT_MAX 0
21 {128, 1896, grp_0}, /* ACH 0 */
33 {40, 0, 0} /* FWCMDQ */
37 1896, /* Group 0 */
40 0 /* WP threshold */
69 {0x44AC, 0x00000000},
70 {0x44B0, 0x00000000},
71 {0x44B4, 0x00000000},
72 {0x44B8, 0x00000000},
73 {0x44BC, 0x00000000},
[all …]

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