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/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt8365.c18 /* 0E4E8SR 4/8/12/16 */
20 /* 0E2E4SR 2/4/6/8 */
23 MTK_DRV_GRP(2, 16, 0, 2, 2)
28 MTK_PIN_DRV_GRP(0, 0x710, 0, 2),
29 MTK_PIN_DRV_GRP(1, 0x710, 0, 2),
30 MTK_PIN_DRV_GRP(2, 0x710, 0, 2),
31 MTK_PIN_DRV_GRP(3, 0x710, 0, 2),
32 MTK_PIN_DRV_GRP(4, 0x710, 4, 2),
33 MTK_PIN_DRV_GRP(5, 0x710, 4, 2),
34 MTK_PIN_DRV_GRP(6, 0x710, 4, 2),
[all …]
/linux/Documentation/userspace-api/media/v4l/
H A Dpipeline.dot6 …scaler [label="{<scaler_0> 0} | Host\nScaler | {<scaler_1> 1} ", shape=Mrecord, style=filled, fill…
7 …frontend [label="{<frontend_0> 0} | Host\nFrontend | {<frontend_1> 1}", shape=Mrecord, style=fille…
8 sensor [label="Sensor | {<sensor_0> 0}", shape=Mrecord, style=filled, fillcolor=aquamarine]
9 io [label="{<io_0> 0} | V4L I/O", shape=Mrecord, style=filled, fillcolor=aquamarine]
13 scaler:scaler_1 -> io:io_0 [color=blue, label="HQ: 1280x720\nHS: 1280x720"]
/linux/Documentation/devicetree/bindings/display/panel/
H A Dsony,tulip-truly-nt35521.yaml7 title: Sony Tulip Truly NT35521 5.24" 1280x720 MIPI-DSI Panel
13 The Sony Tulip Truly NT35521 is a 5.24" 1280x720 MIPI-DSI panel, which
56 #size-cells = <0>;
58 panel@0 {
60 reg = <0>;
H A Drocktech,jh057n00900.yaml29 # Powkiddy RGB30 3.0" 720x720 TFT LCD panel
67 #size-cells = <0>;
68 panel@0 {
70 reg = <0>;
/linux/include/dt-bindings/clock/
H A Dam4.h8 #define AM4_CLKCTRL_OFFSET 0x20
12 #define AM4_L3S_TSC_CLKCTRL_OFFSET 0x120
14 #define AM4_L3S_TSC_ADC_TSC_CLKCTRL AM4_L3S_TSC_CLKCTRL_INDEX(0x120)
17 #define AM4_L4_WKUP_AON_CLKCTRL_OFFSET 0x228
19 #define AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x228)
20 #define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230)
23 #define AM4_L4_WKUP_CLKCTRL_OFFSET 0x220
25 #define AM4_L4_WKUP_L4_WKUP_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x220)
26 #define AM4_L4_WKUP_TIMER1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x328)
27 #define AM4_L4_WKUP_WD_TIMER2_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x338)
[all …]
/linux/drivers/gpu/drm/
H A Ddrm_edid.c70 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
98 #define MICROSOFT_IEEE_OUI 0xca125c
112 #define LEVEL_DMT 0
133 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60),
135 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
136 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC),
139 EDID_QUIRK('B', 'N', 'Q', 0x78d6, EDID_QUIRK_FORCE_8BPC),
142 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC),
145 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC),
148 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC),
[all …]
/linux/Documentation/fb/
H A Dviafb.modes256 # 0 chars 7 lines
268 timings 14667 216 0 14 7 64 4 hsync high vsync high endmode
487 # 0 chars 0 lines
499 timings 8825 280 0 16 0 88 8 endmode mode "1152x720-60"
524 hsync high vsync high endmode mode "1200x720-60"
530 timings 16260 184 28 18 1 128 3 endmode mode "1280x720-50"
779 # 1280x720, 60 Hz, Non-Interlaced (74.481 MHz dotclock)
796 mode "1280x720-60"
/linux/arch/arm/include/asm/hardware/
H A Dcache-aurora-l2.h14 #define AURORA_SYNC_REG 0x700
15 #define AURORA_RANGE_BASE_ADDR_REG 0x720
16 #define AURORA_FLUSH_PHY_ADDR_REG 0x7f0
17 #define AURORA_INVAL_RANGE_REG 0x774
18 #define AURORA_CLEAN_RANGE_REG 0x7b4
19 #define AURORA_FLUSH_RANGE_REG 0x7f4
23 (0x3 << AURORA_ACR_REPLACEMENT_OFFSET)
25 (0 << AURORA_ACR_REPLACEMENT_OFFSET)
34 #define AURORA_ACR_FORCE_WRITE_POLICY_OFFSET 0
36 (0x3 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
[all …]
/linux/drivers/video/fbdev/sis/
H A Dinit.h70 static const unsigned short ModeIndex_320x200[] = {0x59, 0x41, 0x00, 0x4f};
71 static const unsigned short ModeIndex_320x240[] = {0x50, 0x56, 0x00, 0x53};
72 static const unsigned short ModeIndex_320x240_FSTN[] = {0x5a, 0x5b, 0x00, 0x00}; /* FSTN */
73 static const unsigned short ModeIndex_400x300[] = {0x51, 0x57, 0x00, 0x54};
74 static const unsigned short ModeIndex_512x384[] = {0x52, 0x58, 0x00, 0x5c};
75 static const unsigned short ModeIndex_640x400[] = {0x2f, 0x5d, 0x00, 0x5e};
76 static const unsigned short ModeIndex_640x480[] = {0x2e, 0x44, 0x00, 0x62};
77 static const unsigned short ModeIndex_720x480[] = {0x31, 0x33, 0x00, 0x35};
78 static const unsigned short ModeIndex_720x576[] = {0x32, 0x34, 0x00, 0x36};
79 static const unsigned short ModeIndex_768x576[] = {0x5f, 0x60, 0x00, 0x61};
[all …]
/linux/Documentation/admin-guide/media/
H A Dvimc.rst36 media-ctl -d platform:vimc -V '"Sensor A":0[fmt:SBGGR8_1X8/640x480]'
37 media-ctl -d platform:vimc -V '"Debayer A":0[fmt:SBGGR8_1X8/640x480]'
38 media-ctl -d platform:vimc -V '"Scaler":0[fmt:RGB888_1X24/640x480]'
39 media-ctl -d platform:vimc -V '"Scaler":0[crop:(100,50)/400x150]'
42 v4l2-ctl -z platform:vimc -d "Raw Capture 0" -v pixelformat=BA81
65 - entity 28: Lens A (0 pad, 0 link)
66 type V4L2 subdev subtype Lens flags 0
68 - entity 29: Lens B (0 pad, 0 link)
69 type V4L2 subdev subtype Lens flags 0
72 focus_absolute: 0
[all …]
/linux/include/linux/usb/
H A Dusb338x.h19 #define SCRATCH 0x0b
36 #define USB3380_EP_CFG_MASK_IN ((0x3 << IN_ENDPOINT_TYPE) | \
38 #define USB3380_EP_CFG_MASK_OUT ((0x3 << OUT_ENDPOINT_TYPE) | \
45 #define DEVICE_CLASS 0
48 #define U1_SYSTEM_EXIT_LATENCY 0
51 #define U1_DEVICE_EXIT_LATENCY 0
55 #define USB_L1_LPM_SUPPORT 0
58 #define BEST_EFFORT_LATENCY_TOLERANCE 0
66 #define SERIAL_NUMBER_STRING_ENABLE 0
79 #define GPEP0_TIMEOUT_ENABLE 0
[all …]
/linux/drivers/video/fbdev/
H A Dsm712fb.c71 .red = {16, 8, 0},
72 .green = {8, 8, 0},
73 .blue = {0, 8, 0},
78 .nonstd = 0,
88 .type_aux = 0,
89 .xpanstep = 0,
90 .ypanstep = 0,
91 .ywrapstep = 0,
102 {"0x301", 640, 480, 8},
103 {"0x303", 800, 600, 8},
[all …]
/linux/arch/sh/kernel/cpu/sh4a/
H A Dsetup-shx3.c20 * This intentionally only registers SCIF ports 0, 1, and 3. SCIF 2
34 DEFINE_RES_MEM(0xffc30000, 0x100),
35 DEFINE_RES_IRQ(evt2irq(0x700)),
36 DEFINE_RES_IRQ(evt2irq(0x720)),
37 DEFINE_RES_IRQ(evt2irq(0x760)),
38 DEFINE_RES_IRQ(evt2irq(0x740)),
43 .id = 0,
57 DEFINE_RES_MEM(0xffc40000, 0x100),
58 DEFINE_RES_IRQ(evt2irq(0x780)),
59 DEFINE_RES_IRQ(evt2irq(0x7a0)),
[all …]
H A Dsetup-sh7786.c35 DEFINE_RES_MEM(0xffea0000, 0x100),
36 DEFINE_RES_IRQ(evt2irq(0x700)),
37 DEFINE_RES_IRQ(evt2irq(0x720)),
38 DEFINE_RES_IRQ(evt2irq(0x760)),
39 DEFINE_RES_IRQ(evt2irq(0x740)),
44 .id = 0,
62 DEFINE_RES_MEM(0xffeb0000, 0x100),
63 DEFINE_RES_IRQ(evt2irq(0x780)),
67 DEFINE_RES_MEM(0xffeb0000, 0x100),
69 DEFINE_RES_IRQ(0),
[all …]
/linux/drivers/gpu/drm/loongson/
H A Dlsdc_pixpll.c21 /* Byte 0 ~ Byte 3 */
22 unsigned div_out : 7; /* 6 : 0 Output clock divider */
78 {74250, 1280, 720, 60, 22, 49, 3}, /* 1280x720@60Hz */
79 /* 1280x720@50Hz */
147 * Return 0 if success, return -1 if not found.
157 for (i = 0; i < num; ++i) { in lsdc_pixpll_find()
165 return 0; in lsdc_pixpll_find()
189 * Return 0 if a set of parameter is found, otherwise return the error
204 return 0; in lsdc_pixel_pll_compute()
209 unsigned int diff = 0; in lsdc_pixel_pll_compute()
[all …]
/linux/drivers/gpu/drm/radeon/
H A Dr600_reg.h31 #define R600_PCIE_PORT_INDEX 0x0038
32 #define R600_PCIE_PORT_DATA 0x003c
34 #define R600_RCU_INDEX 0x0100
35 #define R600_RCU_DATA 0x0104
37 #define R600_UVD_CTX_INDEX 0xf4a0
38 #define R600_UVD_CTX_DATA 0xf4a4
40 #define R600_MC_VM_FB_LOCATION 0x2180
41 #define R600_MC_FB_BASE_MASK 0x0000FFFF
42 #define R600_MC_FB_BASE_SHIFT 0
43 #define R600_MC_FB_TOP_MASK 0xFFFF0000
[all …]
/linux/arch/sh/kernel/cpu/sh3/
H A Dsetup-sh7705.c20 UNUSED = 0,
36 INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720),
37 INTC_VECT(DMAC, 0x800), INTC_VECT(DMAC, 0x820),
38 INTC_VECT(DMAC, 0x840), INTC_VECT(DMAC, 0x860),
39 INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0),
40 INTC_VECT(SCIF0, 0x8e0),
41 INTC_VECT(SCIF2, 0x900), INTC_VECT(SCIF2, 0x920),
42 INTC_VECT(SCIF2, 0x960),
43 INTC_VECT(ADC_ADI, 0x980),
44 INTC_VECT(USB, 0xa20), INTC_VECT(USB, 0xa40),
[all …]
H A Dsetup-sh770x.c24 UNUSED = 0,
36 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
37 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
38 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
39 INTC_VECT(RTC, 0x4c0),
40 INTC_VECT(SCI, 0x4e0), INTC_VECT(SCI, 0x500),
41 INTC_VECT(SCI, 0x520), INTC_VECT(SCI, 0x540),
42 INTC_VECT(WDT, 0x560),
43 INTC_VECT(REF, 0x580),
44 INTC_VECT(REF, 0x5a0),
[all …]
/linux/drivers/gpu/host1x/hw/
H A Dhw_host1x02_sync.h29 * <x> value 'r' after being shifted to place its LSB at bit 0.
46 return 0x400 + id * REGISTER_STRIDE; in host1x_sync_syncpt_r()
52 return 0x40 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_cpu0_int_status_r()
58 return 0x60 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_int_disable_r()
64 return 0x68 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_int_enable_cpu0_r()
70 return 0x80 + channel * REGISTER_STRIDE; in host1x_sync_cf_setup_r()
76 return (r >> 0) & 0x3ff; in host1x_sync_cf_setup_base_v()
82 return (r >> 16) & 0x3ff; in host1x_sync_cf_setup_limit_v()
88 return 0xac; in host1x_sync_cmdproc_stop_r()
94 return 0xb0; in host1x_sync_ch_teardown_r()
[all …]
H A Dhw_host1x01_sync.h29 * <x> value 'r' after being shifted to place its LSB at bit 0.
46 return 0x400 + id * REGISTER_STRIDE; in host1x_sync_syncpt_r()
52 return 0x40 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_cpu0_int_status_r()
58 return 0x60 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_int_disable_r()
64 return 0x68 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_int_enable_cpu0_r()
70 return 0x80 + channel * REGISTER_STRIDE; in host1x_sync_cf_setup_r()
76 return (r >> 0) & 0x1ff; in host1x_sync_cf_setup_base_v()
82 return (r >> 16) & 0x1ff; in host1x_sync_cf_setup_limit_v()
88 return 0xac; in host1x_sync_cmdproc_stop_r()
94 return 0xb0; in host1x_sync_ch_teardown_r()
[all …]
/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_mipi_dsi_regs.h11 #define LINKSR 0x010
13 #define LINKSR_HSBUSY (1 << 0)
18 #define TXVMSETR 0x180
19 #define TXVMSETR_SYNSEQ_PULSES (0 << 16)
24 #define TXVMSETR_VSEN_DIS (0 << 4)
26 #define TXVMSETR_HFPBPEN_DIS (0 << 2)
28 #define TXVMSETR_HBPBPEN_DIS (0 << 1)
29 #define TXVMSETR_HSABPEN_EN (1 << 0)
30 #define TXVMSETR_HSABPEN_DIS (0 << 0)
32 #define TXVMCR 0x190
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx51-pinfunc.h13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
[all …]
H A Dimx35-pinfunc.h13 #define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0
14 #define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0
15 #define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0
16 #define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0
17 #define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0
18 #define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0
19 #define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0
20 #define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0
21 #define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0
22 #define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0
[all …]
H A Dimx6dl-pinfunc.h13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
/linux/drivers/net/ethernet/apple/
H A Dbmac.h17 #define XIFC 0x000 /* low-level interface control */
18 # define TxOutputEnable 0x0001 /* output driver enable */
19 # define XIFLoopback 0x0002 /* Loopback-mode XIF enable */
20 # define MIILoopback 0x0004 /* Loopback-mode MII enable */
21 # define MIILoopbackBits 0x0006
22 # define MIIBuffDisable 0x0008 /* MII receive buffer disable */
23 # define SQETestEnable 0x0010 /* SQE test enable */
24 # define SQETimeWindow 0x03e0 /* SQE time window */
25 # define XIFLanceMode 0x0010 /* Lance mode enable */
26 # define XIFLanceIPG0 0x03e0 /* Lance mode IPG0 */
[all …]

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