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/freebsd/sys/contrib/device-tree/Bindings/thermal/
H A Dnvidia,tegra30-tsensor.yaml67 reg = <0x70014000 0x500>;
68 interrupts = <0 102 4>;
/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dfsl-imx-sdma.txt33 0 MCU domain SSI
63 0 High
74 val is the value of the bit (0 or 1).
80 reg = <0x83fb0000 0x4000>;
93 reg = <0x70014000 0x4000>;
96 dmas = <&sdma 24 1 0>,
97 <&sdma 25 1 0>;
109 fsl,sdma-event-remap = <0 15 1>, <0 16 1>;
113 - <0 15 1> means that the offset is 0, so GPR0 is the register of the
116 - <0 16 1> means that the offset is 0, so GPR0 is the register of the
/freebsd/sys/dts/arm/
H A Dimx51x.dtsi42 #size-cells = <0>;
44 cpu@0 {
47 reg = <0x0>;
50 d-cache-size = <0x8000>;
51 i-cache-size = <0x8000>;
53 timebase-frequency = <0>;
54 bus-frequency = <0>;
55 clock-frequency = <0>;
71 reg = <0xe0000000 0x00004000>;
84 * E0000000 E0003FFF 0x4000 TZIC
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/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx51.dtsi46 reg = <0xe0000000 0x4000>;
52 #clock-cells = <0>;
58 #clock-cells = <0>;
59 clock-frequency = <0>;
64 #clock-cells = <0>;
65 clock-frequency = <0>;
70 #clock-cells = <0>;
77 #size-cells = <0>;
78 cpu: cpu@0 {
[all...]
/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra30.dtsi20 reg = <0x80000000 0x0>;
26 reg = <0x00003000 0x00000800>, /* PADS registers */
27 <0x00003800 0x00000200>, /* AFI registers */
28 <0x10000000 0x10000000>; /* configuration space */
35 interrupt-map-mask = <0 0
[all...]