Lines Matching +full:0 +full:x70014000
42 #size-cells = <0>;
44 cpu@0 {
47 reg = <0x0>;
50 d-cache-size = <0x8000>;
51 i-cache-size = <0x8000>;
53 timebase-frequency = <0>;
54 bus-frequency = <0>;
55 clock-frequency = <0>;
71 reg = <0xe0000000 0x00004000>;
84 * E0000000 E0003FFF 0x4000 TZIC
93 ranges = <0x70000000 0x70000000 0x14000000>;
103 /* 73FD4000 0x4000 CCM */
106 /* 83F80000 0x4000 DPLLIP1 */
107 /* 83F84000 0x4000 DPLLIP2 */
108 /* 83F88000 0x4000 DPLLIP3 */
109 reg = <0x73fd4000 0x4000
110 0x83F80000 0x4000
111 0x83F84000 0x4000
112 0x83F88000 0x4000>;
122 /* 73F84000 0x4000 GPIO1 */
125 reg = <0x73f84000 0x4000>;
135 /* 73F88000 0x4000 GPIO2 */
138 reg = <0x73f88000 0x4000>;
147 /* 73F8C000 0x4000 GPIO3 */
150 reg = <0x73f8c000 0x4000>;
159 /* 73F90000 0x4000 GPIO4 */
162 reg = <0x73f90000 0x4000>;
178 /* 70004000 0x4000 ESDHC 1 */
181 reg = <0x70004000 0x4000>;
186 /* 70008000 0x4000 ESDHC 2 */
189 reg = <0x70008000 0x4000>;
194 /* 7000C000 0x4000 UART 3 */
197 reg = <0x7000c000 0x4000>;
202 /* 70010000 0x4000 eCSPI1 */
205 #size-cells = <0>;
207 reg = <0x70010000 0x4000>;
212 /* 70014000 0x4000 SSI2 irq30 */
215 reg = <0x70014000 0x4000>;
220 /* 70020000 0x4000 ESDHC 3 */
223 reg = <0x70020000 0x4000>;
228 /* 70024000 0x4000 ESDHC 4 */
231 reg = <0x70024000 0x4000>;
236 /* 70028000 0x4000 SPDIF */
239 /* 70030000 0x4000 PATA (PORT UDMA) irq70 */
241 /* 70034000 0x4000 SLM */
242 /* 70038000 0x4000 HSI2C */ /* 64 HS-I2C */
243 /* 7003C000 0x4000 SPBA */
246 usbphy0: usbphy@0 {
253 reg = <0x73f80000 0x0200>;
255 fsl,usbmisc = <&usbmisc 0>;
262 reg = <0x73f80200 0x0200>;
270 reg = <0x73f80400 0x0200>;
278 reg = <0x73f80600 0x0200>;
287 reg = <0x73f80800 0x200>;
290 /* 73F98000 0x4000 WDOG1 */
293 reg = <0x73f98000 0x4000>;
298 /* 73F9C000 0x4000 WDOG2 (TZ) */
301 reg = <0x73f9c000 0x4000>;
306 /* 73F94000 0x4000 KPP */
309 reg = <0x73f94000 0x4000>;
314 /* 73FA0000 0x4000 GPT */
317 reg = <0x73fa0000 0x4000>;
322 /* 73FA4000 0x4000 SRTC */
326 reg = <0x73fa4000 0x4000>;
331 /* 73FA8000 0x4000 IOMUXC */
334 reg = <0x73fa8000 0x4000>;
338 /* 73FAC000 0x4000 EPIT1 */
341 reg = <0x73fac000 0x4000>;
346 /* 73FB0000 0x4000 EPIT2 */
349 reg = <0x73fb0000 0x4000>;
354 /* 73FB4000 0x4000 PWM1 */
357 reg = <0x73fb4000 0x4000>;
362 /* 73FB8000 0x4000 PWM2 */
365 reg = <0x73fb8000 0x4000>;
370 /* 73FBC000 0x4000 UART 1 */
373 reg = <0x73fbc000 0x4000>;
378 /* 73FC0000 0x4000 UART 2 */
381 reg = <0x73fc0000 0x4000>;
386 /* 73FC4000 0x4000 USBOH3 */
390 reg = <0x73fc4000 0x4000>;
395 /* 73FD0000 0x4000 SRC */
398 reg = <0x73fd0000 0x4000>;
402 /* 73FD8000 0x4000 GPC */
405 reg = <0x73fd8000 0x4000>;
419 /* 83F94000 0x4000 AHBMAX */
420 /* 83F98000 0x4000 IIM */
426 /* 83F9C000 0x4000 CSU */
432 /* 83FA0000 0x4000 TIGERP_PLATFORM_NE_32K_256K */
441 /* 83FA4000 0x4000 OWIRE irq88 */
442 /* 83FA8000 0x4000 FIRI irq93 */
443 /* 83FAC000 0x4000 eCSPI2 */
446 #size-cells = <0>;
448 reg = <0x83fac000 0x4000>;
453 /* 83FB0000 0x4000 SDMA */
456 reg = <0x83fb0000 0x4000>;
460 /* 83FB4000 0x4000 SCC */
465 /* 83FB8000 0x4000 ROMCP */
466 /* 83FBC000 0x4000 RTIC */
472 /* 83FC0000 0x4000 CSPI */
475 #size-cells = <0>;
477 reg = <0x83fc0000 0x4000>;
482 /* 83FC4000 0x4000 I2C2 */
485 #size-cells = <0>;
487 reg = <0x83fc4000 0x4000>;
492 /* 83FC8000 0x4000 I2C1 */
495 #size-cells = <0>;
497 reg = <0x83fc8000 0x4000>;
502 /* 83FCC000 0x4000 SSI1 */
506 reg = <0x83fcc000 0x4000>;
511 /* 83FD0000 0x4000 AUDMUX */
514 reg = <0x83fd4000 0x4000>;
518 /* 83FD8000 0x4000 EMI1 */
527 /* 83FE0000 0x4000 PATA (PORT PIO) */
531 reg = <0x83fe0000 0x4000>;
537 /* 83FE4000 0x4000 SIM */
541 /* 83FE8000 0x4000 SSI3 */
545 reg = <0x83fe8000 0x4000>;
550 /* 83FEC000 0x4000 FEC */
553 reg = <0x83fec000 0x4000>;
558 /* 83FF0000 0x4000 TVE */
560 /* 83FF4000 0x4000 VPU */
564 /* 83FF8000 0x4000 SAHARA Lite */
565 /* 19 SAHARA SAHARA host 0 (TrustZone) Intr Lite */
580 0x5e000000 0x08000 /* CM */
581 0x5e008000 0x08000 /* IDMAC */
582 0x5e018000 0x08000 /* DP */
583 0x5e020000 0x08000 /* IC */
584 0x5e028000 0x08000 /* IRT */
585 0x5e030000 0x08000 /* CSI0 */
586 0x5e038000 0x08000 /* CSI1 */
587 0x5e040000 0x08000 /* DI0 */
588 0x5e048000 0x08000 /* DI1 */
589 0x5e050000 0x08000 /* SMFC */
590 0x5e058000 0x08000 /* DC */
591 0x5e060000 0x08000 /* DMFC */
592 0x5e068000 0x08000 /* VDI */
593 0x5f000000 0x20000 /* CPMEM */
594 0x5f020000 0x20000 /* LUT */
595 0x5f040000 0x20000 /* SRM */
596 0x5f060000 0x20000 /* TPM */
597 0x5f080000 0x20000 /* DCTMPL */