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Searched +full:0 +full:x62000 (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/clk/qcom/
H A Dgcc-sar2130p.c53 .offset = 0x0,
56 .enable_reg = 0x62018,
57 .enable_mask = BIT(0),
70 { 0x1, 2 },
75 .offset = 0x0,
92 .offset = 0x1000,
95 .enable_reg = 0x62018,
109 .offset = 0x4000,
112 .enable_reg = 0x62018,
126 .offset = 0x5000,
[all …]
H A Dgcc-qcs8300.c60 .offset = 0x0,
63 .enable_reg = 0x4b028,
64 .enable_mask = BIT(0),
77 { 0x1, 2 },
82 .offset = 0x0,
99 .offset = 0x1000,
102 .enable_reg = 0x4b028,
116 .offset = 0x4000,
119 .enable_reg = 0x4b028,
133 .offset = 0x7000,
[all …]
H A Dgcc-sa8775p.c74 .offset = 0x0,
77 .enable_reg = 0x4b028,
78 .enable_mask = BIT(0),
89 { 0x1, 2 },
94 .offset = 0x0,
111 .offset = 0x1000,
114 .enable_reg = 0x4b028,
126 .offset = 0x4000,
129 .enable_reg = 0x4b028,
141 .offset = 0x5000,
[all …]
H A Dgcc-msm8916.c45 .l_reg = 0x21004,
46 .m_reg = 0x21008,
47 .n_reg = 0x2100c,
48 .config_reg = 0x21010,
49 .mode_reg = 0x21000,
50 .status_reg = 0x2101c,
63 .enable_reg = 0x45000,
64 .enable_mask = BIT(0),
76 .l_reg = 0x20004,
77 .m_reg = 0x20008,
[all …]
H A Dgcc-msm8939.c53 .l_reg = 0x21004,
54 .m_reg = 0x21008,
55 .n_reg = 0x2100c,
56 .config_reg = 0x21010,
57 .mode_reg = 0x21000,
58 .status_reg = 0x2101c,
71 .enable_reg = 0x45000,
72 .enable_mask = BIT(0),
84 .l_reg = 0x20004,
85 .m_reg = 0x20008,
[all …]
/linux/Documentation/devicetree/bindings/interconnect/
H A Dqcom,rpm.yaml48 reg = <0x00400000 0x62000>;
/linux/arch/arm/mach-omap2/
H A Domap44xx.h17 #define L4_44XX_BASE 0x4a000000
18 #define L4_WK_44XX_BASE 0x4a300000
19 #define L4_PER_44XX_BASE 0x48000000
20 #define L4_EMU_44XX_BASE 0x54000000
21 #define L3_44XX_BASE 0x44000000
22 #define OMAP44XX_EMIF1_BASE 0x4c000000
23 #define OMAP44XX_EMIF2_BASE 0x4d000000
24 #define OMAP44XX_DMM_BASE 0x4e000000
25 #define OMAP4430_32KSYNCT_BASE 0x4a304000
26 #define OMAP4430_CM1_BASE 0x4a004000
[all …]
H A Domap34xx.h17 #define L4_34XX_BASE 0x48000000
18 #define L4_WK_34XX_BASE 0x48300000
19 #define L4_PER_34XX_BASE 0x49000000
20 #define L4_EMU_34XX_BASE 0x54000000
21 #define L3_34XX_BASE 0x68000000
23 #define L4_WK_AM33XX_BASE 0x44C00000
25 #define OMAP3430_32KSYNCT_BASE 0x48320000
26 #define OMAP3430_CM_BASE 0x48004800
27 #define OMAP3430_PRM_BASE 0x48306800
28 #define OMAP343X_SMS_BASE 0x6C000000
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Dintel_audio_regs.h11 #define G4X_AUD_CNTL_ST _MMIO(0x620B4)
16 #define G4X_HDMIW_HDMIEDID _MMIO(0x6210C)
18 #define _IBX_HDMIW_HDMIEDID_A 0xE2050
19 #define _IBX_HDMIW_HDMIEDID_B 0xE2150
22 #define _IBX_AUD_CNTL_ST_A 0xE20B4
23 #define _IBX_AUD_CNTL_ST_B 0xE21B4
29 #define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0)
31 #define IBX_ELD_VALID(port) REG_BIT(((port) - 1) * 4 + 0)
33 #define _CPT_HDMIW_HDMIEDID_A 0xE5050
34 #define _CPT_HDMIW_HDMIEDID_B 0xE5150
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Dam4372.dtsi20 memory@0 {
22 reg = <0 0>;
42 #size-cells = <0>;
43 cpu: cpu@0 {
47 reg = <0>;
77 opp-supported-hw = <0xFF 0x01>;
85 opp-supported-hw = <0xFF 0x04>;
92 opp-supported-hw = <0xFF 0x08>;
99 opp-supported-hw = <0xFF 0x10>;
106 opp-supported-hw = <0xFF 0x20>;
[all …]
/linux/drivers/interconnect/qcom/
H A Dsc7280.c168 .port_offsets = { 0x7000 },
170 .urg_fwd = 0,
182 .port_offsets = { 0x11000 },
184 .urg_fwd = 0,
196 .port_offsets = { 0x8000 },
198 .urg_fwd = 0,
218 .port_offsets = { 0xc000 },
220 .urg_fwd = 0,
232 .port_offsets = { 0xe000 },
234 .urg_fwd = 0,
[all …]
/linux/drivers/gpu/drm/gma500/
H A Dpsb_intel_reg.h11 #define GPIOA 0x5010
12 #define GPIOB 0x5014
13 #define GPIOC 0x5018
14 #define GPIOD 0x501c
15 #define GPIOE 0x5020
16 #define GPIOF 0x5024
17 #define GPIOG 0x5028
18 #define GPIOH 0x502c
19 # define GPIO_CLOCK_DIR_MASK (1 << 0)
20 # define GPIO_CLOCK_DIR_IN (0 << 1)
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_1_8_0_offset.h29 // base address: 0x60000
30 …DAGB0_RDCLI0 0x0000
31 …e regDAGB0_RDCLI0_BASE_IDX 0
32 …DAGB0_RDCLI1 0x0001
33 …e regDAGB0_RDCLI1_BASE_IDX 0
34 …DAGB0_RDCLI2 0x0002
35 …e regDAGB0_RDCLI2_BASE_IDX 0
36 …DAGB0_RDCLI3 0x0003
37 …e regDAGB0_RDCLI3_BASE_IDX 0
38 …DAGB0_RDCLI4 0x0004
[all …]