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/linux/arch/arm64/boot/dts/qcom/
H A Dqcs8300-pmics.dtsi10 pmm8620au_0: pmic@0 {
12 reg = <0x0 SPMI_USID>;
14 #size-cells = <0>;
18 reg = <0x6100>, <0x6200>;
20 interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>;
26 reg = <0x8800>;
28 gpio-ranges = <&pmm8620au_0_gpios 0 0 12>;
37 reg = <0x2 SPMI_USID>;
39 #size-cells = <0>;
43 reg = <0x8800>;
[all …]
H A Dpm4125.dtsi12 pmic@0 {
14 reg = <0x0 SPMI_USID>;
16 #size-cells = <0>;
20 reg = <0x800>;
24 interrupts-extended = <&spmi_bus 0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
32 interrupts-extended = <&spmi_bus 0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
41 reg = <0x1100>;
47 reg = <0x1500>;
48 interrupts = <0x0 0x15 0x00 IRQ_TYPE_EDGE_RISING>,
49 <0x0 0x15 0x01 IRQ_TYPE_EDGE_BOTH>,
[all …]
H A Dsa8540p-pmics.dtsi11 pmm8540a: pmic@0 {
13 reg = <0x0 SPMI_USID>;
15 #size-cells = <0>;
19 reg = <0x6000>, <0x6100>;
21 interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
27 reg = <0xc000>;
29 gpio-ranges = <&pmm8540a_gpios 0 0 10>;
38 reg = <0x4 SPMI_USID>;
40 #size-cells = <0>;
44 reg = <0xb110>;
[all …]
H A Dpm8953.dtsi17 hysteresis = <0>;
23 hysteresis = <0>;
29 hysteresis = <0>;
38 pmic@0 {
40 reg = <0 SPMI_USID>;
42 #size-cells = <0>;
46 reg = <0x800>;
47 mode-bootloader = <0x2>;
48 mode-recovery = <0x1>;
52 interrupts = <0x00 0x08 0 IRQ_TYPE_EDGE_BOTH>;
[all …]
H A Dpm8998.dtsi34 pm8998_lsid0: pmic@0 {
36 reg = <0x0 SPMI_USID>;
38 #size-cells = <0>;
43 reg = <0x800>;
44 mode-bootloader = <0x2>;
45 mode-recovery = <0x1>;
49 interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
57 interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
66 reg = <0x2400>;
67 interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
[all …]
H A Dpmm8155au_1.dtsi21 hysteresis = <0>;
27 hysteresis = <0>;
33 hysteresis = <0>;
42 pmic@0 {
44 reg = <0x0 SPMI_USID>;
46 #size-cells = <0>;
50 reg = <0x0800>;
53 interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>;
64 reg = <0x2400>;
65 interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
[all …]
H A Dpmp8074.dtsi7 pmic@0 {
9 reg = <0x0 SPMI_USID>;
11 #size-cells = <0>;
15 reg = <0x3100>;
16 interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
18 #size-cells = <0>;
21 channel@0 {
86 reg = <0x6000>, <0x6100>;
88 interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
95 reg = <0xc000>;
[all …]
H A Dpm8937.dtsi13 polling-delay-passive = <0>;
14 polling-delay = <0>;
20 hysteresis = <0>;
26 hysteresis = <0>;
32 hysteresis = <0>;
41 pmic@0 {
43 reg = <0x0 SPMI_USID>;
45 #size-cells = <0>;
49 reg = <0x800>;
50 mode-bootloader = <0x2>;
[all …]
H A Dpm8994.dtsi32 pmic@0 {
34 reg = <0x0 SPMI_USID>;
36 #size-cells = <0>;
40 reg = <0x6000>, <0x6100>;
42 interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
47 reg = <0x800>;
48 mode-bootloader = <0x2>;
49 mode-recovery = <0x1>;
53 interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
61 interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
[all …]
H A Dpms405.dtsi35 pms405_0: pms405@0 {
37 reg = <0x0 SPMI_USID>;
39 #size-cells = <0>;
43 reg = <0xc000>;
45 gpio-ranges = <&pms405_gpios 0 0 12>;
53 reg = <0x0800>;
54 mode-bootloader = <0x2>;
55 mode-recovery = <0x1>;
59 interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
68 reg = <0x2400>;
[all …]
H A Dpm6125.dtsi19 hysteresis = <0>;
25 hysteresis = <0>;
31 hysteresis = <0>;
40 pmic@0 {
42 reg = <0x0 SPMI_USID>;
44 #size-cells = <0>;
48 reg = <0x800>;
49 mode-bootloader = <0x2>;
50 mode-recovery = <0x1>;
54 interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>;
[all …]
H A Dpm6150.dtsi22 hysteresis = <0>;
28 hysteresis = <0>;
37 pm6150_lsid0: pmic@0 {
39 reg = <0x0 SPMI_USID>;
41 #size-cells = <0>;
45 reg = <0x800>;
46 mode-bootloader = <0x2>;
47 mode-recovery = <0x1>;
51 interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
59 interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
[all …]
H A Dpm8950.dtsi15 pmic@0 {
17 reg = <0x0 SPMI_USID>;
19 #size-cells = <0>;
23 reg = <0x0800>;
24 mode-bootloader = <0x2>;
25 mode-recovery = <0x1>;
29 interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
37 interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
46 reg = <0x2400>;
47 interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>;
[all …]
H A Dpm660.dtsi37 pmic@0 {
39 reg = <0x0 SPMI_USID>;
41 #size-cells = <0>;
45 reg = <0x6000>, <0x6100>;
47 interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
52 reg = <0x800>;
53 mode-bootloader = <0x2>;
54 mode-recovery = <0x1>;
58 interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
68 interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
[all …]
/linux/Documentation/devicetree/bindings/rtc/
H A Dqcom-pm8xxx-rtc.yaml80 #size-cells = <0>;
82 pmic@0 {
84 reg = <0x0 SPMI_USID>;
86 #size-cells = <0>;
90 reg = <0x6000>, <0x6100>;
92 interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
/linux/arch/arm/boot/dts/qcom/
H A Dpma8084.dtsi9 pma8084_0: pma8084@0 {
11 reg = <0x0 SPMI_USID>;
13 #size-cells = <0>;
17 reg = <0x6000>,
18 <0x6100>;
20 interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
25 reg = <0x800>;
29 interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
38 reg = <0xc000>;
40 gpio-ranges = <&pma8084_gpios 0 0 22>;
[all …]
H A Dpm8226.dtsi11 polling-delay = <0>;
38 pm8226_0: pm8226@0 {
40 reg = <0x0 SPMI_USID>;
42 #size-cells = <0>;
46 reg = <0x800>;
50 interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
58 interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
67 reg = <0x1000>;
68 interrupts = <0x0 0x10 7 IRQ_TYPE_EDGE_BOTH>,
69 <0x0 0x10 5 IRQ_TYPE_EDGE_BOTH>,
[all …]
H A Dpm8941.dtsi11 polling-delay = <0>;
39 pm8941_0: pm8941@0 {
41 reg = <0x0 SPMI_USID>;
43 #size-cells = <0>;
47 reg = <0x6000>,
48 <0x6100>;
50 interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
55 reg = <0x800>;
59 interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
66 interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dqoriq-sec4.0-0.dtsi2 * QorIQ Sec/Crypto 4.0 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v4.0";
40 reg = <0x300000 0x10000>;
41 ranges = <0 0x300000 0x10000>;
42 interrupts = <92 2 0 0>;
45 compatible = "fsl,sec-v4.0-job-ring";
46 reg = <0x1000 0x1000>;
47 interrupts = <88 2 0 0>;
51 compatible = "fsl,sec-v4.0-job-ring";
52 reg = <0x2000 0x1000>;
[all …]
H A Dqoriq-sec5.0-0.dtsi2 * QorIQ Sec/Crypto 5.0 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
40 reg = <0x300000 0x10000>;
41 ranges = <0 0x300000 0x10000>;
42 interrupts = <92 2 0 0>;
45 compatible = "fsl,sec-v5.0-job-ring",
46 "fsl,sec-v4.0-job-ring";
47 reg = <0x1000 0x1000>;
48 interrupts = <88 2 0 0>;
52 compatible = "fsl,sec-v5.0-job-ring",
[all …]
H A Dqoriq-sec4.2-0.dtsi2 * QorIQ Sec/Crypto 4.2 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
40 reg = <0x300000 0x10000>;
41 ranges = <0 0x300000 0x10000>;
42 interrupts = <92 2 0 0>;
46 "fsl,sec-v4.0-job-ring";
47 reg = <0x1000 0x1000>;
48 interrupts = <88 2 0 0>;
53 "fsl,sec-v4.0-job-ring";
54 reg = <0x2000 0x1000>;
[all …]
H A Dqoriq-sec5.3-0.dtsi2 * QorIQ Sec/Crypto 5.3 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v5.3", "fsl,sec-v5.0", "fsl,sec-v4.0";
40 reg = <0x300000 0x10000>;
41 ranges = <0 0x300000 0x10000>;
42 interrupts = <92 2 0 0>;
46 "fsl,sec-v5.0-job-ring",
47 "fsl,sec-v4.0-job-ring";
48 reg = <0x1000 0x1000>;
49 interrupts = <88 2 0 0>;
54 "fsl,sec-v5.0-job-ring",
[all …]
H A Dqoriq-sec5.2-0.dtsi2 * QorIQ Sec/Crypto 5.2 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v5.2", "fsl,sec-v5.0", "fsl,sec-v4.0";
40 reg = <0x300000 0x10000>;
41 ranges = <0 0x300000 0x10000>;
42 interrupts = <92 2 0 0>;
46 "fsl,sec-v5.0-job-ring",
47 "fsl,sec-v4.0-job-ring";
48 reg = <0x1000 0x1000>;
49 interrupts = <88 2 0 0>;
54 "fsl,sec-v5.0-job-ring",
[all …]
/linux/sound/soc/codecs/
H A Drt711-sdca-sdw.h15 { 0x201a, 0x00 },
16 { 0x201e, 0x00 },
17 { 0x201f, 0x00 },
18 { 0x2020, 0x00 },
19 { 0x2021, 0x00 },
20 { 0x2022, 0x00 },
21 { 0x2023, 0x00 },
22 { 0x2024, 0x00 },
23 { 0x2025, 0x01 },
24 { 0x2026, 0x00 },
[all …]
/linux/arch/arm/mach-s5pv210/
H A Dregs-clock.h12 #define S3C_ADDR_BASE 0xF6000000
14 #define S3C_VA_SYS S3C_ADDR(0x00100000)
18 #define S5P_APLL_LOCK S5P_CLKREG(0x00)
19 #define S5P_MPLL_LOCK S5P_CLKREG(0x08)
20 #define S5P_EPLL_LOCK S5P_CLKREG(0x10)
21 #define S5P_VPLL_LOCK S5P_CLKREG(0x20)
23 #define S5P_APLL_CON S5P_CLKREG(0x100)
24 #define S5P_MPLL_CON S5P_CLKREG(0x108)
25 #define S5P_EPLL_CON S5P_CLKREG(0x110)
26 #define S5P_EPLL_CON1 S5P_CLKREG(0x114)
[all …]

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