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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dnvidia,tegra210-car.txt27 reg = <0x60006000 0x1000>;
43 #size-cells = <0>;
48 #clock-cells = <0>;
H A Dnvidia,tegra30-car.txt27 reg = <0x60006000 0x1000>;
43 #size-cells = <0>;
45 osc: clock@0 {
47 reg = <0>;
48 #clock-cells = <0>;
55 #clock-cells = <0>;
H A Dnvidia,tegra114-car.txt27 reg = <0x60006000 0x1000>;
43 #size-cells = <0>;
45 osc: clock@0 {
47 reg = <0>;
48 #clock-cells = <0>;
55 #clock-cells = <0>;
H A Dnvidia,tegra20-car.txt27 reg = <0x60006000 0x1000>;
43 #size-cells = <0>;
45 osc: clock@0 {
47 reg = <0>;
48 #clock-cells = <0>;
55 #clock-cells = <0>;
H A Dnvidia,tegra20-car.yaml89 reg = <0x60006000 0x1000>;
H A Dnvidia,tegra124-car.yaml49 "^emc-timings-[0-9]+$":
59 "^timing-[0-9]+$":
107 reg = <0x60006000 0x1000>;
H A Dnvidia,tegra124-car.txt51 reg = <0x60006000 0x1000>;
68 #size-cells = <0>;
70 osc: clock@0 {
72 reg = <0>;
73 #clock-cells = <0>;
80 #clock-cells = <0>;
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dcortina,gemini-ethernet.txt23 - port0: contains the resources for ethernet port 0
59 reg = <0x60000000 0x4000>, /* Global registers, queue */
60 <0x60004000 0x2000>, /* V-bit */
61 <0x60006000 0x2000>; /* A-bit */
67 gmac0: ethernet-port@0 {
69 reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */
70 <0x6000a000 0x2000>; /* Port 0 GMAC */
82 reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */
83 <0x6000e000 0x2000>; /* Port 1 GMAC */
H A Dcortina,gemini-ethernet.yaml38 "^ethernet-port@[0-9]+$":
92 #size-cells = <0>;
106 reg = <0x60000000 0x4000>, /* Global registers, queue */
107 <0x60004000 0x2000>, /* V-bit */
108 <0x60006000 0x2000>; /* A-bit */
113 gmac0: ethernet-port@0 {
115 reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */
116 <0x6000a000 0x2000>; /* Port 0 GMAC */
128 reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */
129 <0x6000e000 0x2000>; /* Port 1 GMAC */
/freebsd/sys/contrib/device-tree/Bindings/thermal/
H A Dnvidia,tegra124-soctherm.txt61 TEGRA_SOCTHERM_THROT_LEVEL_NONE (0%)
73 the property is missing. A value of 0 will interrupt on every OC alarm.
78 the counter is cleared and filter is rearmed. Default value is 0.
81 is 0.
106 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
107 0x0 0x60006000 0x0 0x400 /* CAR reg_base */
159 nvidia,throttle-period-us = <0>;
171 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
172 0x0 0x70040000 0x0 0x200>; /* CCROC reg_base */;
/freebsd/sys/contrib/device-tree/src/arm/gemini/
H A Dgemini.dtsi23 pinctrl-0 = <&pflash_default_pins>;
31 reg = <0x40000000 0x1000>;
39 offset = <0x0c>;
41 mask = <0xC0000000>;
49 pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
159 reg = <0x41000000 0x1000>;
168 reg = <0x42000000 0x100>;
173 pinctrl-0 = <&uart_default_pins>;
179 reg = <0x43000000 0x1000>;
193 reg = <0x45000000 0x100>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra124.dtsi21 reg = <0x0 0x80000000 0x0 0x0>;
27 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
28 <0x0 0x0100380
[all...]
H A Dtegra114.dtsi17 reg = <0x80000000 0x0>;
22 reg = <0x40000000 0x40000>;
25 ranges = <0 0x40000000 0x40000>;
28 reg = <0x400 0x3fc00>;
35 reg = <0x5000000
[all...]
H A Dtegra20.dtsi17 memory@0 {
19 reg = <0 0>;
24 reg = <0x40000000 0x40000>;
27 ranges = <0 0x40000000 0x40000>;
30 reg = <0x400 0x3fc0
[all...]
H A Dtegra30.dtsi20 reg = <0x80000000 0x0>;
26 reg = <0x00003000 0x00000800>, /* PADS registers */
27 <0x00003800 0x00000200>, /* AFI registers */
28 <0x10000000 0x10000000>; /* configuration space */
35 interrupt-map-mask = <0 0
[all...]
/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra210.dtsi21 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
22 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
23 <0x0 0x0200000
[all...]
H A Dtegra132.dtsi22 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
23 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
24 <0x0 0x0200000
[all...]