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Searched +full:0 +full:x60005000 (Results 1 – 9 of 9) sorted by relevance

/linux/Documentation/devicetree/bindings/timer/
H A Dnvidia,tegra-timer.yaml25 A list of 14 interrupts; one per each timer channels 0 through 13
117 reg = <0x60005000 0x400>;
118 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
119 <0 1 IRQ_TYPE_LEVEL_HIGH>,
120 <0 41 IRQ_TYPE_LEVEL_HIGH>,
121 <0 42 IRQ_TYPE_LEVEL_HIGH>,
122 <0 121 IRQ_TYPE_LEVEL_HIGH>,
123 <0 122 IRQ_TYPE_LEVEL_HIGH>;
133 reg = <0x60005000 0x400>;
135 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
/linux/arch/arm/mach-tegra/
H A Diomap.h16 #define TEGRA_IRAM_BASE 0x40000000
19 #define TEGRA_ARM_PERIF_BASE 0x50040000
22 #define TEGRA_ARM_INT_DIST_BASE 0x50041000
25 #define TEGRA_TMR1_BASE 0x60005000
28 #define TEGRA_TMR2_BASE 0x60005008
31 #define TEGRA_TMRUS_BASE 0x60005010
34 #define TEGRA_TMR3_BASE 0x60005050
37 #define TEGRA_TMR4_BASE 0x60005058
40 #define TEGRA_CLK_RESET_BASE 0x60006000
43 #define TEGRA_FLOW_CTRL_BASE 0x60007000
[all …]
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra114.dtsi17 reg = <0x80000000 0x0>;
22 reg = <0x40000000 0x40000>;
25 ranges = <0 0x40000000 0x40000>;
28 reg = <0x400 0x3fc00>;
35 reg = <0x50000000 0x00028000>;
48 ranges = <0x54000000 0x54000000 0x01000000>;
52 reg = <0x54140000 0x00040000>;
63 reg = <0x54180000 0x00040000>;
73 reg = <0x54200000 0x00040000>;
83 nvidia,head = <0>;
[all …]
H A Dtegra20.dtsi17 memory@0 {
19 reg = <0 0>;
24 reg = <0x40000000 0x40000>;
27 ranges = <0 0x40000000 0x40000>;
30 reg = <0x400 0x3fc00>;
37 reg = <0x50000000 0x00024000>;
51 ranges = <0x54000000 0x54000000 0x04000000>;
55 reg = <0x54040000 0x00040000>;
67 reg = <0x54080000 0x00040000>;
79 reg = <0x540c0000 0x00040000>;
[all …]
H A Dtegra124.dtsi21 reg = <0x0 0x80000000 0x0 0x0>;
27 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
28 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
29 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
36 interrupt-map-mask = <0 0 0 0>;
37 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
39 bus-range = <0x00 0xff>;
43 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
44 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
45 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
[all …]
H A Dtegra30.dtsi20 reg = <0x80000000 0x0>;
26 reg = <0x00003000 0x00000800>, /* PADS registers */
27 <0x00003800 0x00000200>, /* AFI registers */
28 <0x10000000 0x10000000>; /* configuration space */
35 interrupt-map-mask = <0 0 0 0>;
36 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
38 bus-range = <0x00 0xff>;
42 ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00001000>, /* port 0 configuration space */
43 <0x02000000 0 0x00001000 0x00001000 0 0x00001000>, /* port 1 configuration space */
44 <0x02000000 0 0x00004000 0x00004000 0 0x00001000>, /* port 2 configuration space */
[all …]
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra132.dtsi22 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
23 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
24 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
31 interrupt-map-mask = <0 0 0 0>;
32 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
34 bus-range = <0x00 0xff>;
38 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
39 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
40 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
41 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
[all …]
H A Dtegra210.dtsi21 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
22 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
23 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
30 interrupt-map-mask = <0 0 0 0>;
31 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
33 bus-range = <0x00 0xff>;
37 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
38 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
39 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
40 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsa8775p.dtsi27 #clock-cells = <0>;
32 #clock-cells = <0>;
38 #size-cells = <0>;
40 CPU0: cpu@0 {
43 reg = <0x0 0x0>;
45 qcom,freq-domain = <&cpufreq_hw 0>;
65 reg = <0x0 0x100>;
67 qcom,freq-domain = <&cpufreq_hw 0>;
82 reg = <0x0 0x200>;
84 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]