Lines Matching +full:0 +full:x60005000
22 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
23 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
24 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
31 interrupt-map-mask = <0 0 0 0>;
32 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
34 bus-range = <0x00 0xff>;
38 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
39 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
40 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
41 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
42 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
55 pci@1,0 {
57 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
58 reg = <0x000800 0 0 0 0>;
59 bus-range = <0x00 0xff>;
69 pci@2,0 {
71 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
72 reg = <0x001000 0 0 0 0>;
73 bus-range = <0x00 0xff>;
87 reg = <0x0 0x50000000 0x0 0x00034000>;
101 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
105 reg = <0x0 0x54200000 0x0 0x00040000>;
114 nvidia,head = <0>;
119 reg = <0x0 0x54240000 0x0 0x00040000>;
133 reg = <0x0 0x54280000 0x0 0x00040000>;
145 reg = <0x0 0x54540000 0x0 0x00040000>;
160 reg = <0x0 0x545c0000 0x0 0x00040000>;
171 #size-cells = <0>;
180 reg = <0x0 0x50041000 0x0 0x1000>,
181 <0x0 0x50042000 0x0 0x2000>,
182 <0x0 0x50044000 0x0 0x2000>,
183 <0x0 0x50046000 0x0 0x2000>;
191 reg = <0x0 0x57000000 0x0 0x01000000>,
192 <0x0 0x58000000 0x0 0x01000000>;
206 reg = <0x0 0x60004000 0x0 0x100>,
207 <0x0 0x60004100 0x0 0x100>,
208 <0x0 0x60004200 0x0 0x100>,
209 <0x0 0x60004300 0x0 0x100>,
210 <0x0 0x60004400 0x0 0x100>;
218 reg = <0x0 0x60005000 0x0 0x400>;
219 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
231 reg = <0x0 0x60006000 0x0 0x1000>;
239 reg = <0x0 0x60007000 0x0 0x1000>;
244 reg = <0x0 0x6000c800 0x0 0x400>;
259 reg = <0x0 0x6000d000 0x0 0x1000>;
276 reg = <0x0 0x60020000 0x0 0x1400>;
318 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
319 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */
324 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
325 <0x0 0x70003000 0x0 0x434>, /* Mux registers */
326 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
339 reg = <0x0 0x70006000 0x0 0x40>;
351 reg = <0x0 0x70006040 0x0 0x40>;
363 reg = <0x0 0x70006200 0x0 0x40>;
375 reg = <0x0 0x70006300 0x0 0x40>;
387 reg = <0x0 0x7000a000 0x0 0x100>;
397 reg = <0x0 0x7000c000 0x0 0x100>;
400 #size-cells = <0>;
412 reg = <0x0 0x7000c400 0x0 0x100>;
415 #size-cells = <0>;
427 reg = <0x0 0x7000c500 0x0 0x100>;
430 #size-cells = <0>;
442 reg = <0x0 0x7000c700 0x0 0x100>;
445 #size-cells = <0>;
457 reg = <0x0 0x7000d000 0x0 0x100>;
460 #size-cells = <0>;
472 reg = <0x0 0x7000d100 0x0 0x100>;
475 #size-cells = <0>;
487 reg = <0x0 0x7000d400 0x0 0x200>;
490 #size-cells = <0>;
502 reg = <0x0 0x7000d600 0x0 0x200>;
505 #size-cells = <0>;
517 reg = <0x0 0x7000d800 0x0 0x200>;
520 #size-cells = <0>;
532 reg = <0x0 0x7000da00 0x0 0x200>;
535 #size-cells = <0>;
547 reg = <0x0 0x7000dc00 0x0 0x200>;
550 #size-cells = <0>;
562 reg = <0x0 0x7000de00 0x0 0x200>;
565 #size-cells = <0>;
577 reg = <0x0 0x7000e000 0x0 0x100>;
585 reg = <0x0 0x7000e400 0x0 0x400>;
593 reg = <0x0 0x7000f800 0x0 0x400>;
602 reg = <0x0 0x70019000 0x0 0x1000>;
615 reg = <0x0 0x7001b000 0x0 0x1000>;
622 #interconnect-cells = <0>;
627 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
628 <0x0 0x70020000 0x0 0x7000>; /* SATA */
643 reg = <0x0 0x70030000 0x0 0x10000>;
658 reg = <0x0 0x70090000 0x0 0x8000>,
659 <0x0 0x70098000 0x0 0x1000>,
660 <0x0 0x70099000 0x0 0x1000>;
694 reg = <0x0 0x7009f000 0x0 0x1000>;
703 usb2-0 {
705 #phy-cells = <0>;
710 #phy-cells = <0>;
715 #phy-cells = <0>;
724 ulpi-0 {
726 #phy-cells = <0>;
735 hsic-0 {
737 #phy-cells = <0>;
742 #phy-cells = <0>;
751 pcie-0 {
753 #phy-cells = <0>;
758 #phy-cells = <0>;
763 #phy-cells = <0>;
768 #phy-cells = <0>;
773 #phy-cells = <0>;
782 sata-0 {
784 #phy-cells = <0>;
791 usb2-0 {
803 hsic-0 {
811 usb3-0 {
823 reg = <0x0 0x700b0000 0x0 0x200>;
834 reg = <0x0 0x700b0200 0x0 0x200>;
845 reg = <0x0 0x700b0400 0x0 0x200>;
856 reg = <0x0 0x700b0600 0x0 0x200>;
867 reg = <0x0 0x700e2000 0x0 0x600>, /* 0: SOC_THERM reg_base */
868 <0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */
892 reg = <0x0 0x70300000 0x0 0x200>,
893 <0x0 0x70300800 0x0 0x800>,
894 <0x0 0x70300200 0x0 0x600>;
944 reg = <0x0 0x70301000 0x0 0x100>;
955 reg = <0x0 0x70301100 0x0 0x100>;
966 reg = <0x0 0x70301200 0x0 0x100>;
977 reg = <0x0 0x70301300 0x0 0x100>;
988 reg = <0x0 0x70301400 0x0 0x100>;
1000 reg = <0x0 0x7d000000 0x0 0x4000>;
1013 reg = <0x0 0x7d000000 0x0 0x4000>,
1014 <0x0 0x7d000000 0x0 0x4000>;
1023 #phy-cells = <0>;
1024 nvidia,hssync-start-delay = <0>;
1029 nvidia,xcvr-lsfslew = <0>;
1035 nvidia,pmc = <&tegra_pmc 0>;
1041 reg = <0x0 0x7d004000 0x0 0x4000>;
1054 reg = <0x0 0x7d004000 0x0 0x4000>,
1055 <0x0 0x7d000000 0x0 0x4000>;
1064 #phy-cells = <0>;
1065 nvidia,hssync-start-delay = <0>;
1070 nvidia,xcvr-lsfslew = <0>;
1081 reg = <0x0 0x7d008000 0x0 0x4000>;
1094 reg = <0x0 0x7d008000 0x0 0x4000>,
1095 <0x0 0x7d000000 0x0 0x4000>;
1104 #phy-cells = <0>;
1105 nvidia,hssync-start-delay = <0>;
1110 nvidia,xcvr-lsfslew = <0>;
1121 #size-cells = <0>;
1123 cpu@0 {
1126 reg = <0>;
1139 polling-delay = <0>;
1167 polling-delay-passive = <0>;
1168 polling-delay = <0>;
1196 polling-delay = <0>;
1224 polling-delay-passive = <0>;
1225 polling-delay = <0>;