Home
last modified time | relevance | path

Searched +full:0 +full:x600 (Results 1 – 25 of 429) sorted by relevance

12345678910>>...18

/linux/Documentation/admin-guide/media/
H A Dimx7.rst41 virtual channel 0. This module is compliant to previous version of Samsung
48 sensor with a parallel interface or from MIPI CSI-2 virtual channel 0. It has
78 an output of 800x600, and BGGR 10 bit bayer format:
83 media-ctl -l "'ov2680 1-0036':0 -> 'imx7-mipi-csis.0':0[1]"
84 media-ctl -l "'imx7-mipi-csis.0':1 -> 'csi-mux':1[1]"
85 media-ctl -l "'csi-mux':2 -> 'csi':0[1]"
86 media-ctl -l "'csi':1 -> 'csi capture':0[1]"
89 media-ctl -V "'ov2680 1-0036':0 [fmt:SBGGR10_1X10/800x600 field:none]"
90 media-ctl -V "'csi-mux':1 [fmt:SBGGR10_1X10/800x600 field:none]"
91 media-ctl -V "'csi-mux':2 [fmt:SBGGR10_1X10/800x600 field:none]"
[all …]
/linux/drivers/video/fbdev/
H A Dmacmodes.h20 #define VMODE_NVRAM 0
29 #define VMODE_800_600_56 9 /* 800x600, 56Hz */
30 #define VMODE_800_600_60 10 /* 800x600, 60Hz */
31 #define VMODE_800_600_72 11 /* 800x600, 72Hz */
32 #define VMODE_800_600_75 12 /* 800x600, 75Hz */
48 #define CMODE_8 0 /* 8 bits/pixel */
68 #define NV_VMODE 0x140f
69 #define NV_CMODE 0x1410
H A Dcontrolfb.h97 * 3.9064MHz * 2**clock_params[2] * clock_params[1] / clock_params[0].
106 #define CTRLFB_OFF 16 /* position of pixel 0 in frame buffer */
113 int m[2]; /* 0: 2MB vram, 1: 4MB vram */
128 {{ 2, 2}}, /* 800x600, 56Hz */
129 {{ 2, 2}}, /* 800x600, 60Hz */
130 {{ 2, 2}}, /* 800x600, 72Hz */
131 {{ 2, 2}}, /* 800x600, 75Hz */
138 {{ 0, 1}}, /* 1280x960, 75Hz */
139 {{ 0, 1}}, /* 1280x1024, 75Hz */
141 {{ 0, 1}}, /* 1600x1024, 60Hz */
H A Dvalkyriefb.h79 * 3.9064MHz * 2**clock_params[2] * clock_params[1] / clock_params[0].
103 { 1024, 0 },
122 { 1024, 0 },
130 { 1024, 0 },
139 { 832, 0 },
143 /* Register values for 800x600, 72Hz mode (11) */
147 { 800, 0 },
151 /* Register values for 800x600, 60Hz mode (10) */
H A Dplatinumfb.h54 * F = 14.3MHz * c0 / (c1 & 0x1f) / (1 << (c1 >> 5))
55 * Newer ones use the values in clocksel[0], for which the formula
57 * F = 15MHz * c0 / ((c1 & 0x1f) + 2) / (1 << (c1 >> 5))
69 #define DIV2 0x20
70 #define DIV4 0x40
71 #define DIV8 0x60
72 #define DIV16 0x80
76 0x5c00,
78 { 0xffc, 4, 0, 0, 0, 0, 0x428, 0,
79 0, 0xb3, 0xd3, 0x12, 0x1a5, 0x23, 0x28, 0x2d,
[all …]
/linux/Documentation/fb/
H A Dviafb.modes182 # 800x600, 60 Hz, Non-Interlaced (40.00 MHz dotclock)
199 mode "800x600-60"
204 # 800x600, 75 Hz, Non-Interlaced (49.50 MHz dotclock)
221 mode "800x600-75"
226 # 800x600, 85 Hz, Non-Interlaced (56.25 MHz dotclock)
243 mode "800x600-85"
248 # 800x600, 100 Hz, Non-Interlaced (67.50 MHz dotclock)
256 # 0 chars 7 lines
265 mode "800x600-100"
268 timings 14667 216 0 14 7 64 4 hsync high vsync high endmode
[all …]
H A Dviafb.rst22 720x576(60 Hz), 800x600(60, 75, 85, 100, 120 Hz),
41 #modprobe viafb viafb_mode=800x600 viafb_bpp=16 viafb_refresh=60
49 - 800x600
59 - 0 : expansion (default)
63 0 : LCD panel with LSB data format input (default)
67 - 0 : Resolution: 640x480, Channel: single, Dithering: Enable
68 - 1 : Resolution: 800x600, Channel: single, Dithering: Enable
84 - 17: Resolution: 1024x600, Channel: single, Dithering: Enable
89 - 0 : No 2D Hardware Acceleration
93 - 0 : viafb_SAMM_ON disable (default)
[all …]
/linux/drivers/video/fbdev/sis/
H A Doem310.h55 0x00,0x00,0x00, /* 800x600 */
56 0x0b,0x0b,0x0b, /* 1024x768 */
57 0x08,0x08,0x08, /* 1280x1024 */
58 0x00,0x00,0x00, /* 640x480 (unknown) */
59 0x00,0x00,0x00, /* 1024x600 (unknown) */
60 0x00,0x00,0x00, /* 1152x864 (unknown) */
61 0x08,0x08,0x08, /* 1280x960 (guessed) */
62 0x00,0x00,0x00, /* 1152x768 (unknown) */
63 0x08,0x08,0x08, /* 1400x1050 */
64 0x08,0x08,0x08, /* 1280x768 (guessed) */
[all …]
H A Dinit.h70 static const unsigned short ModeIndex_320x200[] = {0x59, 0x41, 0x00, 0x4f};
71 static const unsigned short ModeIndex_320x240[] = {0x50, 0x56, 0x00, 0x53};
72 static const unsigned short ModeIndex_320x240_FSTN[] = {0x5a, 0x5b, 0x00, 0x00}; /* FSTN */
73 static const unsigned short ModeIndex_400x300[] = {0x51, 0x57, 0x00, 0x54};
74 static const unsigned short ModeIndex_512x384[] = {0x52, 0x58, 0x00, 0x5c};
75 static const unsigned short ModeIndex_640x400[] = {0x2f, 0x5d, 0x00, 0x5e};
76 static const unsigned short ModeIndex_640x480[] = {0x2e, 0x44, 0x00, 0x62};
77 static const unsigned short ModeIndex_720x480[] = {0x31, 0x33, 0x00, 0x35};
78 static const unsigned short ModeIndex_720x576[] = {0x32, 0x34, 0x00, 0x36};
79 static const unsigned short ModeIndex_768x576[] = {0x5f, 0x60, 0x00, 0x61};
[all …]
/linux/drivers/video/fbdev/geode/
H A Dlxfb_core.c41 FB_VMODE_NONINTERLACED, 0 },
45 FB_VMODE_NONINTERLACED, 0 },
48 0, FB_VMODE_NONINTERLACED, 0 },
52 FB_VMODE_NONINTERLACED, 0 },
56 FB_VMODE_NONINTERLACED, 0 },
60 FB_VMODE_NONINTERLACED, 0 },
63 0, FB_VMODE_NONINTERLACED, 0 },
66 0, FB_VMODE_NONINTERLACED, 0 },
70 FB_VMODE_NONINTERLACED, 0 },
71 /* 800x600-56 */
[all …]
/linux/arch/xtensa/platforms/xtfpga/include/platform/
H A Dhardware.h37 #define DUART16552_PADDR (XCHAL_KIO_PADDR + 0x0D050020)
40 #define XTFPGA_FPGAREGS_VADDR IOADDR(0x0D020000)
42 #define XTFPGA_CLKFRQ_VADDR (XTFPGA_FPGAREGS_VADDR + 0x04)
44 #define DIP_SWITCHES_VADDR (XTFPGA_FPGAREGS_VADDR + 0x0C)
45 /* Software reset (write 0xdead): */
46 #define XTFPGA_SWRST_VADDR (XTFPGA_FPGAREGS_VADDR + 0x10)
50 #define OETH_REGS_PADDR (XCHAL_KIO_PADDR + 0x0D030000)
51 #define OETH_REGS_SIZE 0x1000
52 #define OETH_SRAMBUFF_PADDR (XCHAL_KIO_PADDR + 0x0D800000)
55 #define OETH_SRAMBUFF_SIZE (5 * 0x600 + 5 * 0x600)
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dsam9x7.dtsi36 #size-cells = <0>;
38 cpu@0 {
40 reg = <0>;
49 #clock-cells = <0>;
55 #clock-cells = <0>;
61 reg = <0x300000 0x10000>;
62 ranges = <0 0x300000 0x10000>;
75 reg = <0x80000000 0x300>;
76 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
86 reg = <0x90000000 0x300>;
[all …]
H A Dlan966x.dtsi27 #size-cells = <0>;
29 cpu@0 {
33 reg = <0x0>;
40 #clock-cells = <0>;
46 #clock-cells = <0>;
52 #clock-cells = <0>;
58 #clock-cells = <0>;
68 reg = <0xe00c00a8 0x38>, <0xe00c02cc 0x4>;
90 reg = <0x00200000 0x80000>,
91 <0xe0808000 0x400>;
[all …]
/linux/include/dt-bindings/clock/
H A Dlpc18xx-ccu.h13 #define CLK_APB3_BUS 0x100
14 #define CLK_APB3_I2C1 0x108
15 #define CLK_APB3_DAC 0x110
16 #define CLK_APB3_ADC0 0x118
17 #define CLK_APB3_ADC1 0x120
18 #define CLK_APB3_CAN0 0x128
19 #define CLK_APB1_BUS 0x200
20 #define CLK_APB1_MOTOCON_PWM 0x208
21 #define CLK_APB1_I2C0 0x210
22 #define CLK_APB1_I2S 0x218
[all …]
/linux/drivers/video/fbdev/via/
H A Dlcd.h11 #define VT1631_DEVICE_ID_REG 0x02
12 #define VT1631_DEVICE_ID 0x92
14 #define VT3271_DEVICE_ID_REG 0x02
15 #define VT3271_DEVICE_ID 0x71
19 #define LCD_PANEL_ID0_640X480 0x00
20 /* Resolution: 800x600, Channel: single, Dithering: Enable */
21 #define LCD_PANEL_ID1_800X600 0x01
23 #define LCD_PANEL_ID2_1024X768 0x02
25 #define LCD_PANEL_ID3_1280X768 0x03
27 #define LCD_PANEL_ID4_1280X1024 0x04
[all …]
/linux/drivers/gpu/drm/loongson/
H A Dlsdc_pixpll.c22 /* Byte 0 ~ Byte 3 */
23 unsigned div_out : 7; /* 6 : 0 Output clock divider */
86 {51200, 1024, 600, 60, 25, 64, 5}, /* 1024x600@60Hz */
89 {49500, 800, 600, 75, 40, 99, 5}, /* 800x600@75Hz */
90 {50000, 800, 600, 72, 44, 88, 4}, /* 800x600@72Hz */
91 {40000, 800, 600, 60, 30, 36, 3}, /* 800x600@60Hz */
92 {36000, 800, 600, 56, 50, 72, 4}, /* 800x600@56Hz */
148 * Return 0 if success, return -1 if not found.
158 for (i = 0; i < num; ++i) { in lsdc_pixpll_find()
166 return 0; in lsdc_pixpll_find()
[all …]
/linux/drivers/video/fbdev/i810/
H A Di810_dvt.c21 { 25000, 0x0013, 0x0003, 0x40, 0x5F, 0x4F, 0x50, 0x82, 0x51, 0x9D,
22 0x0B, 0x10, 0x40, 0xE9, 0x0B, 0xDF, 0x50, 0xE7, 0x04, 0x02,
23 0x01, 0x01, 0x01, 0x00, 0x01, 0x22002000, 0x22004000, 0x22006000,
24 0x22002000, 0x22004000, 0x22006000, 0xC0 },
27 { 28000, 0x0053, 0x0010, 0x40, 0x61, 0x4F, 0x4F, 0x85, 0x52, 0x9A,
28 0xF2, 0x10, 0x40, 0xE0, 0x03, 0xDF, 0x50, 0xDF, 0xF3, 0x01,
29 0x01, 0x01, 0x01, 0x00, 0x01, 0x22002000, 0x22004000, 0x22005000,
30 0x22002000, 0x22004000, 0x22005000, 0xC0 },
33 { 31000, 0x0013, 0x0002, 0x40, 0x63, 0x4F, 0x4F, 0x87, 0x52, 0x97,
34 0x06, 0x0F, 0x40, 0xE8, 0x0B, 0xDF, 0x50, 0xDF, 0x07, 0x02,
[all …]
/linux/arch/arm64/boot/dts/broadcom/bcmbca/
H A Dbcm63146.dtsi18 #size-cells = <0>;
20 B53_0: cpu@0 {
23 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
61 #clock-cells = <0>;
67 #clock-cells = <0>;
75 #clock-cells = <0>;
89 ranges = <0x0 0x0 0x81000000 0x8000>;
95 reg = <0x1000 0x1000>,
96 <0x2000 0x2000>,
[all …]
H A Dbcm6813.dtsi18 #size-cells = <0>;
20 B53_0: cpu@0 {
23 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
39 reg = <0x0 0x2>;
47 reg = <0x0 0x3>;
80 #clock-cells = <0>;
86 #clock-cells = <0>;
94 #clock-cells = <0>;
108 ranges = <0x0 0x0 0x81000000 0x8000>;
[all …]
H A Dbcm4912.dtsi18 #size-cells = <0>;
20 B53_0: cpu@0 {
23 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
39 reg = <0x0 0x2>;
47 reg = <0x0 0x3>;
80 #clock-cells = <0>;
86 #clock-cells = <0>;
94 #clock-cells = <0>;
108 ranges = <0x0 0x0 0x81000000 0x8000>;
[all …]
/linux/drivers/net/ethernet/wangxun/libwx/
H A Dwx_mbx.h9 #define WX_PXMAILBOX(i) (0x600 + (4 * (i))) /* i=[0,63] */
10 #define WX_PXMAILBOX_STS BIT(0) /* Initiate message send to VF */
15 #define WX_VXMAILBOX 0x600
16 #define WX_VXMAILBOX_REQ BIT(0) /* Request for PF Ready bit */
27 #define WX_VXMBMEM 0x00C00 /* 16*4B */
28 #define WX_PXMBMEM(i) (0x5000 + (64 * (i))) /* i=[0,63] */
30 #define WX_VFLRE(i) (0x4A0 + (4 * (i))) /* i=[0,1] */
31 #define WX_VFLREC(i) (0x4A8 + (4 * (i))) /* i=[0,1] */
34 #define WX_MBVFICR(i) (0x480 + (4 * (i))) /* i=[0,3] */
35 #define WX_MBVFICR_VFREQ_MASK GENMASK(15, 0)
[all …]
/linux/arch/sh/kernel/cpu/shmobile/
H A Dpm.c41 #define RAM_BASE 0xfd800000 /* RSMEM */
43 #define RAM_BASE 0xe5200000 /* ILRAM */
86 /* part 0: data area */ in sh_mobile_register_self_refresh()
88 sdp->addr.stbcr = 0xa4150020; /* STBCR */ in sh_mobile_register_self_refresh()
89 sdp->addr.bar = 0xa4150040; /* BAR */ in sh_mobile_register_self_refresh()
90 sdp->addr.pteh = 0xff000000; /* PTEH */ in sh_mobile_register_self_refresh()
91 sdp->addr.ptel = 0xff000004; /* PTEL */ in sh_mobile_register_self_refresh()
92 sdp->addr.ttb = 0xff000008; /* TTB */ in sh_mobile_register_self_refresh()
93 sdp->addr.tea = 0xff00000c; /* TEA */ in sh_mobile_register_self_refresh()
94 sdp->addr.mmucr = 0xff000010; /* MMUCR */ in sh_mobile_register_self_refresh()
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm6756.dtsi18 #size-cells = <0>;
20 CA7_0: cpu@0 {
23 reg = <0x0>;
31 reg = <0x1>;
39 reg = <0x2>;
47 reg = <0x3>;
81 #clock-cells = <0>;
87 #clock-cells = <0>;
95 #clock-cells = <0>;
109 ranges = <0 0x81000000 0x8000>;
[all …]
H A Dbcm47622.dtsi18 #size-cells = <0>;
20 CA7_0: cpu@0 {
23 reg = <0x0>;
31 reg = <0x1>;
39 reg = <0x2>;
47 reg = <0x3>;
81 #clock-cells = <0>;
87 #clock-cells = <0>;
95 #clock-cells = <0>;
109 ranges = <0 0x81000000 0x8000>;
[all …]
/linux/drivers/video/fbdev/core/
H A Dmodedb.c40 { NULL, 70, 640, 400, 39721, 40, 24, 39, 9, 96, 2, 0,
44 { NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2, 0,
47 /* 800x600 @ 56 Hz, 35.15 kHz hsync */
48 { NULL, 56, 800, 600, 27777, 128, 24, 22, 1, 72, 2, 0,
52 { NULL, 87, 1024, 768, 22271, 56, 24, 33, 8, 160, 8, 0,
60 { NULL, 72, 640, 480, 31746, 144, 40, 30, 8, 40, 3, 0,
64 { NULL, 75, 640, 480, 31746, 120, 16, 16, 1, 64, 3, 0,
67 /* 800x600 @ 60 Hz, 37.8 kHz hsync */
73 { NULL, 85, 640, 480, 27777, 80, 56, 25, 1, 56, 3, 0,
77 { NULL, 89, 1152, 864, 15384, 96, 16, 110, 1, 216, 10, 0,
[all …]

12345678910>>...18