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/linux/arch/arm/mach-omap2/
H A Ddma.c36 [REVISION] = { 0x0000, 0x00, OMAP_DMA_REG_32BIT },
37 [GCR] = { 0x0078, 0x00, OMAP_DMA_REG_32BIT },
38 [IRQSTATUS_L0] = { 0x0008, 0x00, OMAP_DMA_REG_32BIT },
39 [IRQSTATUS_L1] = { 0x000c, 0x00, OMAP_DMA_REG_32BIT },
40 [IRQSTATUS_L2] = { 0x0010, 0x00, OMAP_DMA_REG_32BIT },
41 [IRQSTATUS_L3] = { 0x0014, 0x00, OMAP_DMA_REG_32BIT },
42 [IRQENABLE_L0] = { 0x0018, 0x00, OMAP_DMA_REG_32BIT },
43 [IRQENABLE_L1] = { 0x001c, 0x00, OMAP_DMA_REG_32BIT },
44 [IRQENABLE_L2] = { 0x0020, 0x00, OMAP_DMA_REG_32BIT },
45 [IRQENABLE_L3] = { 0x0024, 0x00, OMAP_DMA_REG_32BIT },
[all …]
/linux/drivers/net/ethernet/microchip/
H A Denc28j60_hw.h15 * - Register address (bits 0-4)
19 #define ADDR_MASK 0x1F
20 #define BANK_MASK 0x60
21 #define SPRD_MASK 0x80
23 #define EIE 0x1B
24 #define EIR 0x1C
25 #define ESTAT 0x1D
26 #define ECON2 0x1E
27 #define ECON1 0x1F
28 /* Bank 0 registers */
[all …]
H A Dencx24j600_hw.h22 #define BANK_SELECT(bank) (0xC0 | ((bank & (BANK_MASK >> BANK_SHIFT)) << 1))
23 #define B0SEL 0xC0 /* Bank 0 Select */
24 #define B1SEL 0xC2 /* Bank 1 Select */
25 #define B2SEL 0xC4 /* Bank 2 Select */
26 #define B3SEL 0xC6 /* Bank 3 Select */
27 #define SETETHRST 0xCA /* System Reset */
28 #define FCDISABLE 0xE0 /* Flow Control Disable */
29 #define FCSINGLE 0xE2 /* Flow Control Single */
30 #define FCMULTIPLE 0xE4 /* Flow Control Multiple */
31 #define FCCLEAR 0xE6 /* Flow Control Clear */
[all …]
/linux/drivers/mtd/spi-nor/
H A Dissi.c25 return 0; in is25lp256_post_bfpt_fixups()
38 for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) in pm25lv_nor_late_init()
42 return 0; in pm25lv_nor_late_init()
63 .id = SNOR_ID(0x7f, 0x9d, 0x20),
69 .id = SNOR_ID(0x7f, 0x9d, 0x46),
74 .id = SNOR_ID(0x9d, 0x40, 0x13),
79 .id = SNOR_ID(0x9d, 0x60, 0x14),
84 .id = SNOR_ID(0x9d, 0x60, 0x15),
89 .id = SNOR_ID(0x9d, 0x60, 0x16),
94 .id = SNOR_ID(0x9d, 0x60, 0x17),
[all …]
H A Dgigadevice.c29 return 0; in gd25q256_post_bfpt()
38 .id = SNOR_ID(0xc8, 0x40, 0x15),
44 .id = SNOR_ID(0xc8, 0x40, 0x16),
50 .id = SNOR_ID(0xc8, 0x40, 0x17),
56 .id = SNOR_ID(0xc8, 0x40, 0x18),
62 .id = SNOR_ID(0xc8, 0x40, 0x19),
68 .id = SNOR_ID(0xc8, 0x60, 0x16),
74 .id = SNOR_ID(0xc8, 0x60, 0x17),
80 .id = SNOR_ID(0xc8, 0x60, 0x18),
/linux/drivers/soc/qcom/
H A Dspm.c29 #define SPM_CTL_INDEX 0x7f
31 #define SPM_CTL_EN BIT(0)
34 #define SPM_VCTL_VLVL GENMASK(7, 0)
35 #define SPM_PMIC_DATA_0_VLVL GENMASK(7, 0)
36 #define SPM_PMIC_DATA_1_MIN_VSEL GENMASK(5, 0)
91 [SPM_REG_AVS_CTL] = 0x904,
92 [SPM_REG_AVS_LIMIT] = 0x908,
97 .avs_ctl = 0x1010031,
98 .avs_limit = 0x4580458,
103 .avs_ctl = 0x101c031,
[all …]
/linux/drivers/gpib/include/
H A Dgpib_cmd.h12 gpib_command_mask = 0x7f,
18 GTL = 0x1, /* go to local */
19 SDC = 0x4, /* selected device clear */
20 PP_CONFIG = 0x5,
21 GET = 0x8, /* group execute trigger */
22 TCT = 0x9, /* take control */
23 LLO = 0x11, /* local lockout */
24 DCL = 0x14, /* device clear */
25 PPU = 0x15, /* parallel poll unconfigure */
26 SPE = 0x18, /* serial poll enable */
[all …]
/linux/kernel/bpf/preload/iterators/
H A Diterators.lskel-little-endian.h27 int fd = skel_link_create(prog_fd, 0, BPF_TRACE_ITER); in iterators_bpf__dump_bpf_map__attach()
29 if (fd > 0) in iterators_bpf__dump_bpf_map__attach()
38 int fd = skel_link_create(prog_fd, 0, BPF_TRACE_ITER); in iterators_bpf__dump_bpf_prog__attach()
40 if (fd > 0) in iterators_bpf__dump_bpf_prog__attach()
48 int ret = 0; in iterators_bpf__attach()
50 ret = ret < 0 ? ret : iterators_bpf__dump_bpf_map__attach(skel); in iterators_bpf__attach()
51 ret = ret < 0 ? ret : iterators_bpf__dump_bpf_prog__attach(skel); in iterators_bpf__attach()
52 return ret < 0 ? ret : 0; in iterators_bpf__attach()
96 \0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\ in iterators_bpf__load()
97 \0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\ in iterators_bpf__load()
[all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen6/
H A Dl2-cache.json4 "EventCode": "0x60",
6 "UMask": "0x01"
10 "EventCode": "0x60",
12 "UMask": "0x02"
16 "EventCode": "0x60",
18 "UMask": "0x04"
22 "EventCode": "0x60",
24 "UMask": "0x10"
28 "EventCode": "0x60",
30 "UMask": "0x20"
[all …]
/linux/drivers/net/wan/
H A Dwanxlfw.inc_shipped2 0x60,0x00,0x00,0x16,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0xB9,0x40,0x00,0x00,0x00,0x00,0x00,
4 0x10,0x14,0x42,0x80,0x4A,0xB0,0x09,0xB0,0x00,0x00,0x10,0x04,0x67,0x00,0x00,0x0E,
5 0x06,0xB0,0x40,0x00,0x00,0x00,0x09,0xB0,0x00,0x00,0x10,0x04,0x58,0x80,0x0C,0x80,
6 0x00,0x00,0x00,0x10,0x66,0x00,0xFF,0xDE,0x21,0xFC,0x00,0x00,0x16,0xBC,0x00,0x6C,
7 0x21,0xFC,0x00,0x00,0x17,0x5E,0x01,0x00,0x21,0xFC,0x00,0x00,0x16,0xDE,0x01,0x78,
8 0x21,0xFC,0x00,0x00,0x16,0xFE,0x01,0x74,0x21,0xFC,0x00,0x00,0x17,0x1E,0x01,0x70,
9 0x21,0xFC,0x00,0x00,0x17,0x3E,0x01,0x6C,0x21,0xFC,0x00,0x00,0x18,0x4C,0x02,0x00,
10 0x23,0xFC,0x78,0x00,0x00,0x00,0xFF,0xFC,0x15,0x48,0x33,0xFC,0x04,0x80,0xFF,0xFC,
11 0x10,0x26,0x33,0xFC,0x01,0x10,0xFF,0xFC,0x10,0x2A,0x23,0xFC,0x00,0xD4,0x9F,0x40,
[all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen1/
H A Dcache.json4 "EventCode": "0x80",
9 "EventCode": "0x81",
14 "EventCode": "0x82",
19 "EventCode": "0x83",
24 "EventCode": "0x84",
29 "EventCode": "0x85",
34 "EventCode": "0x86",
39 "EventCode": "0x87",
41 "UMask": "0x04"
45 "EventCode": "0x87",
[all …]
/linux/include/sound/
H A Dcs8403.h26 if (bits & 0x01) { /* consumer */ in SND_CS8403_DECODE()
27 if (!(bits & 0x02)) in SND_CS8403_DECODE()
28 diga->status[0] |= IEC958_AES0_NONAUDIO; in SND_CS8403_DECODE()
29 if (!(bits & 0x08)) in SND_CS8403_DECODE()
30 diga->status[0] |= IEC958_AES0_CON_NOT_COPYRIGHT; in SND_CS8403_DECODE()
31 switch (bits & 0x10) { in SND_CS8403_DECODE()
32 case 0x10: diga->status[0] |= IEC958_AES0_CON_EMPHASIS_NONE; break; in SND_CS8403_DECODE()
33 case 0x00: diga->status[0] |= IEC958_AES0_CON_EMPHASIS_5015; break; in SND_CS8403_DECODE()
35 if (!(bits & 0x80)) in SND_CS8403_DECODE()
37 switch (bits & 0x60) { in SND_CS8403_DECODE()
[all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen2/
H A Dcache.json4 "EventCode": "0x60",
6 "UMask": "0x80"
10 "EventCode": "0x60",
12 "UMask": "0x40"
16 "EventCode": "0x60",
18 "UMask": "0x20"
22 "EventCode": "0x60",
24 "UMask": "0x10"
28 "EventCode": "0x60",
30 "UMask": "0x08"
[all …]
/linux/drivers/media/usb/gspca/
H A Dt613.c54 #if 0 /* HDG: broken with my test cam, so lets disable it */
66 #if 0 /* HDG: broken with my test cam, so lets disable it */
77 .priv = 0},
94 0x09, 0x01, 0x12, 0x04, 0x66, 0x8a, 0x80, 0x3c,
95 0x81, 0x22, 0x84, 0x50, 0x8a, 0x78, 0x8b, 0x68,
96 0x8c, 0x88, 0x8e, 0x33, 0x8f, 0x24, 0xaa, 0xb1,
97 0xa2, 0x60, 0xa5, 0x30, 0xa6, 0x3a, 0xa8, 0xe8,
98 0xae, 0x05, 0xb1, 0x00, 0xbb, 0x04, 0xbc, 0x48,
99 0xbe, 0x36, 0xc6, 0x88, 0xe9, 0x00, 0xc5, 0xc0,
100 0x65, 0x0a, 0xbb, 0x86, 0xaf, 0x58, 0xb0, 0x68,
[all …]
/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt8135.c17 #define DRV_BASE1 0x500
18 #define DRV_BASE2 0x510
19 #define PUPD_BASE1 0x400
20 #define PUPD_BASE2 0x450
21 #define R0_BASE1 0x4d0
22 #define R1_BASE1 0x200
23 #define R1_BASE2 0x250
49 MTK_DRV_GRP(2, 16, 0, 2, 2),
53 MTK_DRV_GRP(2, 8, 0, 1, 2),
55 MTK_DRV_GRP(4, 32, 0, 2, 4)
[all …]
H A Dpinctrl-mt8173.c18 #define DRV_BASE 0xb00
21 MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 2, 1, 0), /* KROW0 */
22 MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 6, 5, 4), /* KROW1 */
23 MTK_PIN_PUPD_SPEC_SR(121, 0xe00, 10, 9, 8), /* KROW2 */
24 MTK_PIN_PUPD_SPEC_SR(122, 0xe10, 2, 1, 0), /* KCOL0 */
25 MTK_PIN_PUPD_SPEC_SR(123, 0xe10, 6, 5, 4), /* KCOL1 */
26 MTK_PIN_PUPD_SPEC_SR(124, 0xe10, 10, 9, 8), /* KCOL2 */
28 MTK_PIN_PUPD_SPEC_SR(67, 0xd10, 2, 1, 0), /* ms0 DS */
29 MTK_PIN_PUPD_SPEC_SR(68, 0xd00, 2, 1, 0), /* ms0 RST */
30 MTK_PIN_PUPD_SPEC_SR(66, 0xc10, 2, 1, 0), /* ms0 cmd */
[all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen3/
H A Dcache.json4 "EventCode": "0x60",
6 "UMask": "0x80"
10 "EventCode": "0x60",
12 "UMask": "0x40"
16 "EventCode": "0x60",
18 "UMask": "0x20"
22 "EventCode": "0x60",
24 "UMask": "0x10"
28 "EventCode": "0x60",
30 "UMask": "0x08"
[all …]
/linux/lib/crypto/x86/
H A Dchacha-avx2-x86_64.S12 ROT8: .octa 0x0e0d0c0f0a09080b0605040702010003
13 .octa 0x0e0d0c0f0a09080b0605040702010003
17 ROT16: .octa 0x0d0c0f0e09080b0a0504070601000302
18 .octa 0x0d0c0f0e09080b0a0504070601000302
22 CTRINC: .octa 0x00000003000000020000000100000000
23 .octa 0x00000007000000060000000500000004
27 CTR2BL: .octa 0x00000000000000000000000000000000
28 .octa 0x00000000000000000000000000000001
32 CTR4BL: .octa 0x00000000000000000000000000000002
33 .octa 0x00000000000000000000000000000003
[all …]
/linux/include/linux/mfd/
H A Dtwl4030-audio.h14 #define TWL4030_REG_CODEC_MODE 0x01
15 #define TWL4030_REG_OPTION 0x02
16 #define TWL4030_REG_UNKNOWN 0x03
17 #define TWL4030_REG_MICBIAS_CTL 0x04
18 #define TWL4030_REG_ANAMICL 0x05
19 #define TWL4030_REG_ANAMICR 0x06
20 #define TWL4030_REG_AVADC_CTL 0x07
21 #define TWL4030_REG_ADCMICSEL 0x08
22 #define TWL4030_REG_DIGMIXING 0x09
23 #define TWL4030_REG_ATXL1PGA 0x0A
[all …]
H A Drt5033-private.h13 RT5033_REG_CHG_STAT = 0x00,
14 RT5033_REG_CHG_CTRL1 = 0x01,
15 RT5033_REG_CHG_CTRL2 = 0x02,
16 RT5033_REG_DEVICE_ID = 0x03,
17 RT5033_REG_CHG_CTRL3 = 0x04,
18 RT5033_REG_CHG_CTRL4 = 0x05,
19 RT5033_REG_CHG_CTRL5 = 0x06,
20 RT5033_REG_RT_CTRL0 = 0x07,
21 RT5033_REG_CHG_RESET = 0x08,
22 /* Reserved 0x09~0x18 */
[all …]
/linux/drivers/regulator/
H A Dda9211-regulator.h12 #define DA9211_REG_PAGE_CON 0x00
15 #define DA9211_REG_STATUS_A 0x50
16 #define DA9211_REG_STATUS_B 0x51
17 #define DA9211_REG_EVENT_A 0x52
18 #define DA9211_REG_EVENT_B 0x53
19 #define DA9211_REG_MASK_A 0x54
20 #define DA9211_REG_MASK_B 0x55
21 #define DA9211_REG_CONTROL_A 0x56
24 #define DA9211_REG_GPIO_0_1 0x58
25 #define DA9211_REG_GPIO_2_3 0x59
[all …]
/linux/include/linux/soundwire/
H A Dsdw_intel.h15 #define SDW_SHIM_BASE 0x2C000
16 #define SDW_ALH_BASE 0x2C800
17 #define SDW_SHIM_BASE_ACE 0x38000
18 #define SDW_ALH_BASE_ACE 0x24000
19 #define SDW_LINK_BASE 0x30000
20 #define SDW_LINK_SIZE 0x10000
24 #define SDW_SHIM_LCAP 0x0
25 #define SDW_SHIM_LCAP_LCOUNT_MASK GENMASK(2, 0)
29 #define SDW_SHIM_LCTL 0x4
31 #define SDW_SHIM_LCTL_SPA BIT(0)
[all …]
/linux/fs/nls/
H A Dnls_ascii.c17 /* 0x00*/
18 0x0000, 0x0001, 0x0002, 0x0003,
19 0x0004, 0x0005, 0x0006, 0x0007,
20 0x0008, 0x0009, 0x000a, 0x000b,
21 0x000c, 0x000d, 0x000e, 0x000f,
22 /* 0x10*/
23 0x0010, 0x0011, 0x0012, 0x0013,
24 0x0014, 0x0015, 0x0016, 0x0017,
25 0x0018, 0x0019, 0x001a, 0x001b,
26 0x001c, 0x001d, 0x001e, 0x001f,
[all …]
/linux/arch/arm/mach-footbridge/include/mach/
H A Duncompress.h12 #define DC21285_BASE ((volatile unsigned int *)0x42000160)
13 #define SER0_BASE ((volatile unsigned char *)0x7c0003f8)
18 while ((SER0_BASE[5] & 0x60) != 0x60) in putc()
20 SER0_BASE[0] = c; in putc()
23 DC21285_BASE[0] = c; in putc()
/linux/lib/crypto/tests/
H A Dblake2b-testvecs.h9 .data_len = 0,
11 0x78, 0x6a, 0x02, 0xf7, 0x42, 0x01, 0x59, 0x03,
12 0xc6, 0xc6, 0xfd, 0x85, 0x25, 0x52, 0xd2, 0x72,
13 0x91, 0x2f, 0x47, 0x40, 0xe1, 0x58, 0x47, 0x61,
14 0x8a, 0x86, 0xe2, 0x17, 0xf7, 0x1f, 0x54, 0x19,
15 0xd2, 0x5e, 0x10, 0x31, 0xaf, 0xee, 0x58, 0x53,
16 0x13, 0x89, 0x64, 0x44, 0x93, 0x4e, 0xb0, 0x4b,
17 0x90, 0x3a, 0x68, 0x5b, 0x14, 0x48, 0xb7, 0x55,
18 0xd5, 0x6f, 0x70, 0x1a, 0xfe, 0x9b, 0xe2, 0xce,
24 0x6f, 0x2e, 0xcc, 0x83, 0x53, 0xa3, 0x20, 0x16,
[all …]

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