Lines Matching +full:0 +full:x60
22 #define BANK_SELECT(bank) (0xC0 | ((bank & (BANK_MASK >> BANK_SHIFT)) << 1))
23 #define B0SEL 0xC0 /* Bank 0 Select */
24 #define B1SEL 0xC2 /* Bank 1 Select */
25 #define B2SEL 0xC4 /* Bank 2 Select */
26 #define B3SEL 0xC6 /* Bank 3 Select */
27 #define SETETHRST 0xCA /* System Reset */
28 #define FCDISABLE 0xE0 /* Flow Control Disable */
29 #define FCSINGLE 0xE2 /* Flow Control Single */
30 #define FCMULTIPLE 0xE4 /* Flow Control Multiple */
31 #define FCCLEAR 0xE6 /* Flow Control Clear */
32 #define SETPKTDEC 0xCC /* Decrement Packet Counter */
33 #define DMASTOP 0xD2 /* DMA Stop */
34 #define DMACKSUM 0xD8 /* DMA Start Checksum */
35 #define DMACKSUMS 0xDA /* DMA Start Checksum with Seed */
36 #define DMACOPY 0xDC /* DMA Start Copy */
37 #define DMACOPYS 0xDE /* DMA Start Copy and Checksum with Seed */
38 #define SETTXRTS 0xD4 /* Request Packet Transmission */
39 #define ENABLERX 0xE8 /* Enable RX */
40 #define DISABLERX 0xEA /* Disable RX */
41 #define SETEIE 0xEC /* Enable Interrupts */
42 #define CLREIE 0xEE /* Disable Interrupts */
45 #define RBSEL 0xC8 /* Read Bank Select */
48 #define WGPRDPT 0x60 /* Write EGPRDPT */
49 #define RGPRDPT 0x62 /* Read EGPRDPT */
50 #define WRXRDPT 0x64 /* Write ERXRDPT */
51 #define RRXRDPT 0x66 /* Read ERXRDPT */
52 #define WUDARDPT 0x68 /* Write EUDARDPT */
53 #define RUDARDPT 0x6A /* Read EUDARDPT */
54 #define WGPWRPT 0x6C /* Write EGPWRPT */
55 #define RGPWRPT 0x6E /* Read EGPWRPT */
56 #define WRXWRPT 0x70 /* Write ERXWRPT */
57 #define RRXWRPT 0x72 /* Read ERXWRPT */
58 #define WUDAWRPT 0x74 /* Write EUDAWRPT */
59 #define RUDAWRPT 0x76 /* Read EUDAWRPT */
62 #define RCRCODE 0x00
63 #define WCRCODE 0x40
64 #define BFSCODE 0x80
65 #define BFCCODE 0xA0
68 #define RCRU 0x20 /* Read Control Register Unbanked */
69 #define WCRU 0x22 /* Write Control Register Unbanked */
72 #define BFSU 0x24 /* Bit Field Set Unbanked */
73 #define BFCU 0x26 /* Bit Field Clear Unbanked */
74 #define RGPDATA 0x28 /* Read EGPDATA */
75 #define WGPDATA 0x2A /* Write EGPDATA */
76 #define RRXDATA 0x2C /* Read ERXDATA */
77 #define WRXDATA 0x2E /* Write ERXDATA */
78 #define RUDADATA 0x30 /* Read EUDADATA */
79 #define WUDADATA 0x32 /* Write EUDADATA */
81 #define SFR_REG_COUNT 0xA0
86 * - Register address (bits 0-4)
89 #define ADDR_MASK 0x1F
90 #define BANK_MASK 0x60
94 #define EUDAST 0x16
95 #define EUDAND 0x18
96 #define ESTAT 0x1A
97 #define EIR 0x1C
98 #define ECON1 0x1E
100 /* Bank 0 registers */
101 #define ETXST (0x00 | 0x00)
102 #define ETXLEN (0x02 | 0x00)
103 #define ERXST (0x04 | 0x00)
104 #define ERXTAIL (0x06 | 0x00)
105 #define ERXHEAD (0x08 | 0x00)
106 #define EDMAST (0x0A | 0x00)
107 #define EDMALEN (0x0C | 0x00)
108 #define EDMADST (0x0E | 0x00)
109 #define EDMACS (0x10 | 0x00)
110 #define ETXSTAT (0x12 | 0x00)
111 #define ETXWIRE (0x14 | 0x00)
114 #define EHT1 (0x00 | 0x20)
115 #define EHT2 (0x02 | 0x20)
116 #define EHT3 (0x04 | 0x20)
117 #define EHT4 (0x06 | 0x20)
118 #define EPMM1 (0x08 | 0x20)
119 #define EPMM2 (0x0A | 0x20)
120 #define EPMM3 (0x0C | 0x20)
121 #define EPMM4 (0x0E | 0x20)
122 #define EPMCS (0x10 | 0x20)
123 #define EPMO (0x12 | 0x20)
124 #define ERXFCON (0x14 | 0x20)
127 #define MACON1 (0x00 | 0x40)
128 #define MACON2 (0x02 | 0x40)
129 #define MABBIPG (0x04 | 0x40)
130 #define MAIPG (0x06 | 0x40)
131 #define MACLCON (0x08 | 0x40)
132 #define MAMXFL (0x0A | 0x40)
133 #define MICMD (0x12 | 0x40)
134 #define MIREGADR (0x14 | 0x40)
137 #define MAADR3 (0x00 | 0x60)
138 #define MAADR2 (0x02 | 0x60)
139 #define MAADR1 (0x04 | 0x60)
140 #define MIWR (0x06 | 0x60)
141 #define MIRD (0x08 | 0x60)
142 #define MISTAT (0x0A | 0x60)
143 #define EPAUS (0x0C | 0x60)
144 #define ECON2 (0x0E | 0x60)
145 #define ERXWM (0x10 | 0x60)
146 #define EIE (0x12 | 0x60)
147 #define EIDLED (0x14 | 0x60)
150 #define EGPDATA (0x00 | 0x80)
151 #define ERXDATA (0x02 | 0x80)
152 #define EUDADATA (0x04 | 0x80)
153 #define EGPRDPT (0x06 | 0x80)
154 #define EGPWRPT (0x08 | 0x80)
155 #define ERXRDPT (0x0A | 0x80)
156 #define ERXWRPT (0x0C | 0x80)
157 #define EUDARDPT (0x0E | 0x80)
158 #define EUDAWRPT (0x10 | 0x80)
181 #define PCFULIF (1 << 0)
199 #define RXEN (1 << 0)
207 #define COLCNT_MASK 0xF
224 #define BCEN (1 << 0)
242 #define FULDPX (1 << 0)
249 #define MAIPGH_VAL 0x0C
250 #define MAIPGL_VAL 0x12
256 #define PHREG_MASK 0x1F
260 #define MIIRD (1 << 0)
265 #define BUSY (1 << 0)
283 #define AESLEN0 (1 << 0)
296 #define PCFULIE (1 << 0)
308 #define DEVID_MASK (0x7 << DEVID_SHIFT)
309 #define REVID_SHIFT 0
310 #define REVID_MASK (0x1F << REVID_SHIFT)
313 #define PHCON1 0x00
314 #define PHSTAT1 0x01
315 #define PHANA 0x04
316 #define PHANLPA 0x05
317 #define PHANE 0x06
318 #define PHCON2 0x11
319 #define PHSTAT2 0x1B
320 #define PHSTAT3 0x1F
340 #define EXTREGS (1 << 0)
349 #define SPDDPX_MASK (0x7 << SPDDPX_SHIFT)
353 #define PHANA_DEFAULT 0x05E1
358 #define LPANABL (1 << 0)
360 #define EUDAST_TEST_VAL 0x1234
364 #define ENCX24J600_DEV_ID 0x1
371 #define LED_A_SETTINGS 0xC
374 #define LED_B_SETTINGS 0x8
389 #define SRAM_GP_START 0x0
392 #define SRAM_SIZE 0x6000
420 #define RSV_GETBIT(x, y) (((x) & RSV_BITMASK(y)) ? 1 : 0)
428 /* Put RX buffer at 0 as suggested by the Errata datasheet */
431 #define RXEND_INIT 0x5FFF