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/linux/drivers/pinctrl/sunxi/
H A Dpinctrl-sun50i-h616.c19 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
20 SUNXI_FUNCTION(0x0, "gpio_in"),
21 SUNXI_FUNCTION(0x1, "gpio_out"),
22 SUNXI_FUNCTION(0x2, "emac1"), /* ERXD1 */
23 SUNXI_FUNCTION(0x4, "i2c0"), /* SCK */
24 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */
26 SUNXI_FUNCTION(0x0, "gpio_in"),
27 SUNXI_FUNCTION(0x1, "gpio_out"),
28 SUNXI_FUNCTION(0x2, "emac1"), /* ERXD0 */
29 SUNXI_FUNCTION(0x4, "i2c0"), /* SDA */
[all …]
H A Dpinctrl-suniv-f1c100s.c32 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
33 SUNXI_FUNCTION(0x0, "gpio_in"),
34 SUNXI_FUNCTION(0x1, "gpio_out"),
35 SUNXI_FUNCTION(0x2, "rtp"), /* X1 */
36 SUNXI_FUNCTION(0x4, "i2s"), /* BCLK */
37 SUNXI_FUNCTION(0x5, "uart1"), /* RTS */
38 SUNXI_FUNCTION(0x6, "spi1")), /* CS */
40 SUNXI_FUNCTION(0x0, "gpio_in"),
41 SUNXI_FUNCTION(0x1, "gpio_out"),
42 SUNXI_FUNCTION(0x2, "rtp"), /* X2 */
[all …]
H A Dpinctrl-sun9i-a80.c21 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
22 SUNXI_FUNCTION(0x0, "gpio_in"),
23 SUNXI_FUNCTION(0x1, "gpio_out"),
24 SUNXI_FUNCTION(0x2, "gmac"), /* RXD3 */
25 SUNXI_FUNCTION(0x4, "uart1"), /* TX */
26 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */
28 SUNXI_FUNCTION(0x0, "gpio_in"),
29 SUNXI_FUNCTION(0x1, "gpio_out"),
30 SUNXI_FUNCTION(0x2, "gmac"), /* RXD2 */
31 SUNXI_FUNCTION(0x4, "uart1"), /* RX */
[all …]
H A Dpinctrl-sun50i-h6-r.c22 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
23 SUNXI_FUNCTION(0x0, "gpio_in"),
24 SUNXI_FUNCTION(0x1, "gpio_out"),
25 SUNXI_FUNCTION(0x2, "s_rsb"), /* SCK */
26 SUNXI_FUNCTION(0x3, "s_i2c"), /* SCK */
27 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PL_EINT0 */
29 SUNXI_FUNCTION(0x0, "gpio_in"),
30 SUNXI_FUNCTION(0x1, "gpio_out"),
31 SUNXI_FUNCTION(0x2, "s_rsb"), /* SDA */
32 SUNXI_FUNCTION(0x3, "s_i2c"), /* SDA */
[all …]
H A Dpinctrl-sun50i-h6.c16 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
17 SUNXI_FUNCTION(0x2, "emac")), /* ERXD1 */
19 SUNXI_FUNCTION(0x2, "emac")), /* ERXD0 */
21 SUNXI_FUNCTION(0x2, "emac")), /* ECRS_DV */
23 SUNXI_FUNCTION(0x2, "emac")), /* ERXERR */
25 SUNXI_FUNCTION(0x2, "emac")), /* ETXD1 */
27 SUNXI_FUNCTION(0x2, "emac")), /* ETXD0 */
29 SUNXI_FUNCTION(0x2, "emac")), /* ETXCK */
31 SUNXI_FUNCTION(0x2, "emac")), /* ETXEN */
33 SUNXI_FUNCTION(0x2, "emac")), /* EMDC */
[all …]
H A Dpinctrl-sun6i-a31.c21 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
22 SUNXI_FUNCTION(0x0, "gpio_in"),
23 SUNXI_FUNCTION(0x1, "gpio_out"),
24 SUNXI_FUNCTION(0x2, "gmac"), /* TXD0 */
25 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
27 SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
28 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */
30 SUNXI_FUNCTION(0x0, "gpio_in"),
31 SUNXI_FUNCTION(0x1, "gpio_out"),
32 SUNXI_FUNCTION(0x2, "gmac"), /* TXD1 */
[all …]
H A Dpinctrl-sun50i-a100-r.c17 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
18 SUNXI_FUNCTION(0x0, "gpio_in"),
19 SUNXI_FUNCTION(0x1, "gpio_out"),
20 SUNXI_FUNCTION(0x2, "s_i2c0"), /* SCK */
21 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),
23 SUNXI_FUNCTION(0x0, "gpio_in"),
24 SUNXI_FUNCTION(0x1, "gpio_out"),
25 SUNXI_FUNCTION(0x2, "s_i2c0"), /* SDA */
26 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),
28 SUNXI_FUNCTION(0x0, "gpio_in"),
[all …]
H A Dpinctrl-sun50i-h5.c26 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
27 SUNXI_FUNCTION(0x0, "gpio_in"),
28 SUNXI_FUNCTION(0x1, "gpio_out"),
29 SUNXI_FUNCTION(0x2, "uart2"), /* TX */
30 SUNXI_FUNCTION(0x3, "jtag"), /* MS */
31 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */
33 SUNXI_FUNCTION(0x0, "gpio_in"),
34 SUNXI_FUNCTION(0x1, "gpio_out"),
35 SUNXI_FUNCTION(0x2, "uart2"), /* RX */
36 SUNXI_FUNCTION(0x3, "jtag"), /* CK */
[all …]
/linux/drivers/pinctrl/nuvoton/
H A Dpinctrl-ma35d1.c21 MA35_PIN(0, PA0, 0x80, 0x0,
22 MA35_MUX(0x0, "GPA0"),
23 MA35_MUX(0x2, "UART1_nCTS"),
24 MA35_MUX(0x3, "UART16_RXD"),
25 MA35_MUX(0x6, "NAND_DATA0"),
26 MA35_MUX(0x7, "EBI_AD0"),
27 MA35_MUX(0x9, "EBI_ADR0")),
28 MA35_PIN(1, PA1, 0x80, 0x4,
29 MA35_MUX(0x0, "GPA1"),
30 MA35_MUX(0x2, "UART1_nRTS"),
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7ulp-pinfunc.h15 #define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
16 #define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
17 #define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
18 #define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
19 #define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
20 #define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
21 #define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
22 #define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
23 #define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
24 #define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1
[all …]
H A Dimx50-pinfunc.h13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
H A Dimx7d-pinfunc.h14 #define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
15 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
16 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
17 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
18 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
19 #define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
20 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
21 #define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
22 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
23 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
[all …]
H A Dimx6sx-pinfunc.h13 #define MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x0014 0x035C 0x07A8 0x0 0x1
14 #define MX6SX_PAD_GPIO1_IO00__USDHC1_VSELECT 0x0014 0x035C 0x0000 0x1 0x0
15 #define MX6SX_PAD_GPIO1_IO00__SPDIF_LOCK 0x0014 0x035C 0x0000 0x2 0x0
16 #define MX6SX_PAD_GPIO1_IO00__CCM_WAIT 0x0014 0x035C 0x0000 0x3 0x0
17 #define MX6SX_PAD_GPIO1_IO00__WDOG1_WDOG_ANY 0x0014 0x035C 0x0000 0x4 0x0
18 #define MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x0014 0x035C 0x0000 0x5 0x0
19 #define MX6SX_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5 0x0014 0x035C 0x0000 0x6 0x0
20 #define MX6SX_PAD_GPIO1_IO00__PHY_DTB_1 0x0014 0x035C 0x0000 0x7 0x0
21 #define MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x0018 0x0360 0x07AC 0x0 0x1
22 #define MX6SX_PAD_GPIO1_IO01__USDHC1_RESET_B 0x0018 0x0360 0x0000 0x1 0x0
[all …]
H A Dimx35-pinfunc.h13 #define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0
14 #define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0
15 #define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0
16 #define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0
17 #define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0
18 #define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0
19 #define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0
20 #define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0
21 #define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0
22 #define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0
[all …]
H A Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
/linux/arch/x86/crypto/
H A Daria-aesni-avx-asm_64.S19 ( (((a0) & 1) << 0) | \
29 ( ((l7) << (0 * 8)) | \
172 x4, x5, x6, x7, \ argument
176 vmovdqu (0 * 16)(rio), x0; \
182 vmovdqu (6 * 16)(rio), x6; \
195 x4, x5, x6, x7, \ argument
200 x4, x5, x6, x7, \
205 vmovdqu x0, 0 * 16(mem_ab); \
211 vmovdqu x6, 6 * 16(mem_ab); \
213 vmovdqu y0, 0 * 16(mem_cd); \
[all …]
H A Daria-aesni-avx2-asm_64.S35 ( (((a0) & 1) << 0) | \
45 ( ((l7) << (0 * 8)) | \
188 x4, x5, x6, x7, \ argument
192 vmovdqu (0 * 32)(rio), x0; \
198 vmovdqu (6 * 32)(rio), x6; \
211 x4, x5, x6, x7, \ argument
216 x4, x5, x6, x7, \
221 vmovdqu x0, 0 * 32(mem_ab); \
227 vmovdqu x6, 6 * 32(mem_ab); \
229 vmovdqu y0, 0 * 32(mem_cd); \
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
/linux/arch/arm64/boot/dts/microchip/
H A Dsparx5.dtsi28 #size-cells = <0>;
39 cpu0: cpu@0 {
42 reg = <0x0>;
49 reg = <0x1>;
81 #clock-cells = <0>;
89 reg = <0x6 0x1110000c 0x24>;
94 #clock-cells = <0>;
100 #clock-cells = <0>;
116 reg = <0x6 0x00300000 0x10000>, /* GIC Dist */
117 <0x6 0x00340000 0xc0000>, /* GICR */
[all …]
/linux/arch/arm/mach-mv78xx0/
H A Dmpp.h12 /* MPP number */ ((_num) & 0xff) | \
13 /* MPP select value */ (((_sel) & 0xf) << 8) | \
20 #define MPP_78100_A0_MASK MPP(0, 0x0, 0, 0, 1)
22 #define MPP0_GPIO MPP(0, 0x0, 1, 1, 1)
23 #define MPP0_GE0_COL MPP(0, 0x1, 0, 0, 1)
24 #define MPP0_GE1_TXCLK MPP(0, 0x2, 0, 0, 1)
25 #define MPP0_UNUSED MPP(0, 0x3, 0, 0, 1)
27 #define MPP1_GPIO MPP(1, 0x0, 1, 1, 1)
28 #define MPP1_GE0_RXERR MPP(1, 0x1, 0, 0, 1)
29 #define MPP1_GE1_TXCTL MPP(1, 0x2, 0, 0, 1)
[all …]
/linux/drivers/pinctrl/
H A Dpinctrl-keembay.c22 #define KEEMBAY_GPIO_DATA_OUT 0x000
23 #define KEEMBAY_GPIO_DATA_IN 0x020
24 #define KEEMBAY_GPIO_DATA_IN_RAW 0x040
25 #define KEEMBAY_GPIO_DATA_HIGH 0x060
26 #define KEEMBAY_GPIO_DATA_LOW 0x080
29 #define KEEMBAY_GPIO_INT_CFG 0x000
30 #define KEEMBAY_GPIO_MODE 0x070
36 #define KEEMBAY_GPIO_MODE_SELECT_MASK GENMASK(2, 0)
43 #define KEEMBAY_GPIO_MODE_DEFAULT 0x7
44 #define KEEMBAY_GPIO_MODE_INV_VAL 0x3
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_7_0_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MC_RD_ENABLE_MASK 0x30
36 #define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x4
[all …]
/linux/drivers/pinctrl/mvebu/
H A Dpinctrl-armada-375.c21 MPP_MODE(0,
22 MPP_FUNCTION(0x0, "gpio", NULL),
23 MPP_FUNCTION(0x1, "dev", "ad2"),
24 MPP_FUNCTION(0x2, "spi0", "cs1"),
25 MPP_FUNCTION(0x3, "spi1", "cs1"),
26 MPP_FUNCTION(0x5, "nand", "io2")),
28 MPP_FUNCTION(0x0, "gpio", NULL),
29 MPP_FUNCTION(0x1, "dev", "ad3"),
30 MPP_FUNCTION(0x2, "spi0", "mosi"),
31 MPP_FUNCTION(0x3, "spi1", "mosi"),
[all …]

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