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/linux/arch/arm/boot/dts/st/
H A Dstm32mp135.dtsi13 reg = <0x5a000000 0x400>;
25 reg = <0x5a001000 0x400>;
H A Dstm32mp157.dtsi13 reg = <0x59000000 0x800>;
22 reg = <0x5a000000 0x800>;
32 #size-cells = <0>;
34 port@0 {
35 reg = <0>;
/linux/Documentation/devicetree/bindings/dma/
H A Dsocionext,uniphier-mio-dmac.yaml52 // In the example below, "interrupts = <0 68 4>, <0 68 4>, ..." is not a
57 reg = <0x5a000000 0x1000>;
58 interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
59 <0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>;
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8-ss-dma.dtsi13 #clock-cells = <0>;
22 ranges = <0x5a000000 0x0 0x5a000000 0x1000000>;
26 reg = <0x5a000000 0x10000>;
28 #size-cells = <0>;
37 dmas = <&edma2 1 0 0>, <&edma2 0 0 FSL_EDMA_RX>;
44 reg = <0x5a010000 0x10000>;
46 #size-cells = <0>;
55 dmas = <&edma2 3 0 0>, <&edma2 2 0 FSL_EDMA_RX>;
62 reg = <0x5a020000 0x10000>;
64 #size-cells = <0>;
[all …]
/linux/Documentation/devicetree/bindings/display/
H A Dst,stm32-dsi.yaml55 port@0:
93 reg = <0x5a000000 0x800>;
101 #size-cells = <0>;
105 #size-cells = <0>;
107 port@0 {
108 reg = <0>;
122 panel@0 {
124 reg = <0>;
/linux/drivers/watchdog/
H A Dbcm2835_wdt.c23 #define PM_RSTC 0x1c
24 #define PM_RSTS 0x20
25 #define PM_WDOG 0x24
27 #define PM_PASSWORD 0x5a000000
29 #define PM_WDOG_TIME_SET 0x000fffff
30 #define PM_RSTC_WRCFG_CLR 0xffffffcf
31 #define PM_RSTS_HADWRH_SET 0x00000040
32 #define PM_RSTC_WRCFG_SET 0x00000030
33 #define PM_RSTC_WRCFG_FULL_RESET 0x00000020
34 #define PM_RSTC_RESET 0x00000102
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap4.dtsi40 #size-cells = <0>;
42 cpu@0 {
46 reg = <0x0>;
57 reg = <0x1>;
67 reg = <0x40304000 0xa000>; /* 40k */
74 reg = <0x48241000 0x1000>,
75 <0x48240100 0x0100>;
81 reg = <0x48242000 0x1000>;
89 reg = <0x48240600 0x20>;
98 reg = <0x48281000 0x1000>;
[all …]
H A Ddra7.dtsi60 reg = <0x0 0x48211000 0x0 0x1000>,
61 <0x0 0x48212000 0x0 0x2000>,
62 <0x0 0x48214000 0x0 0x2000>,
63 <0x0 0x48216000 0x0 0x2000>;
72 reg = <0x0 0x48281000 0x0 0x1000>;
78 #size-cells = <0>;
80 cpu0: cpu@0 {
83 reg = <0>;
108 opp-supported-hw = <0xFF 0x01>;
118 opp-supported-hw = <0xFF 0x02>;
[all …]
/linux/sound/soc/codecs/
H A Dcs48l32.h15 #define CS48L32_SILICON_ID 0x48a32
17 #define CS48L32_32K_MCLK1 0
19 #define CS48L32_SFT_RESET_MAGIC 0x5a000000
23 #define CS48L32_SEEN_BOOT_DONE BIT(0)
26 #define CS48L32_ASP_ENABLES1 0x00
27 #define CS48L32_ASP_CONTROL1 0x04
28 #define CS48L32_ASP_CONTROL2 0x08
29 #define CS48L32_ASP_CONTROL3 0x0c
30 #define CS48L32_ASP_FRAME_CONTROL1 0x10
31 #define CS48L32_ASP_FRAME_CONTROL2 0x14
[all …]
/linux/arch/arm/boot/dts/socionext/
H A Duniphier-ld4.dtsi18 #size-cells = <0>;
20 cpu@0 {
23 reg = <0>;
37 #clock-cells = <0>;
42 #clock-cells = <0>;
57 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
58 <0x506c0000 0x400>;
71 reg = <0x54006000 0x100>;
73 #size-cells = <0>;
76 pinctrl-0 = <&pinctrl_spi0>;
[all …]
H A Duniphier-sld8.dtsi18 #size-cells = <0>;
20 cpu@0 {
23 reg = <0>;
37 #clock-cells = <0>;
42 #clock-cells = <0>;
57 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
58 <0x506c0000 0x400>;
71 reg = <0x54006000 0x100>;
73 #size-cells = <0>;
76 pinctrl-0 = <&pinctrl_spi0>;
[all …]
H A Duniphier-pro4.dtsi18 #size-cells = <0>;
20 cpu@0 {
23 reg = <0>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
65 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
66 <0x506c0000 0x400>;
79 reg = <0x54006000 0x100>;
81 #size-cells = <0>;
84 pinctrl-0 = <&pinctrl_spi0>;
[all …]
H A Duniphier-pxs2.dtsi19 #size-cells = <0>;
21 cpu0: cpu@0 {
24 reg = <0>;
112 #clock-cells = <0>;
117 #clock-cells = <0>;
163 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
164 <0x506c0000 0x400>;
179 reg = <0x54006000 0x100>;
181 #size-cells = <0>;
184 pinctrl-0 = <&pinctrl_spi0>;
[all …]
/linux/arch/arm/mach-omap2/
H A Diomap.h33 #define OMAP2_L3_IO_OFFSET 0x90000000
36 #define OMAP2_L4_IO_OFFSET 0xb2000000
39 #define OMAP4_L3_IO_OFFSET 0xb4000000
42 #define AM33XX_L4_WK_IO_OFFSET 0xb5000000
45 #define OMAP4_L3_PER_IO_OFFSET 0xb1100000
48 #define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
58 #define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
61 #define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
65 #define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
70 /* 0x6e000000 --> 0xfe000000 */
[all …]
/linux/drivers/pmdomain/bcm/
H A Dbcm2835-power.c20 #define PM_GNRIC 0x00
21 #define PM_AUDIO 0x04
22 #define PM_STATUS 0x18
23 #define PM_RSTC 0x1c
24 #define PM_RSTS 0x20
25 #define PM_WDOG 0x24
26 #define PM_PADS0 0x28
27 #define PM_PADS2 0x2c
28 #define PM_PADS3 0x30
29 #define PM_PADS4 0x34
[all …]
/linux/arch/arm64/boot/dts/socionext/
H A Duniphier-ld11.dtsi20 #size-cells = <0>;
33 cpu0: cpu@0 {
36 reg = <0 0x000>;
46 reg = <0 0x001>;
102 #clock-cells = <0>;
126 reg = <0x0 0x81000000 0x0 0x01000000>;
131 soc@0 {
135 ranges = <0 0 0 0xffffffff>;
140 reg = <0x54006000 0x100>;
142 #size-cells = <0>;
[all …]
/linux/include/sound/
H A Dcs35l41.h16 #define CS35L41_FIRSTREG 0x00000000
17 #define CS35L41_LASTREG 0x03804FE8
18 #define CS35L41_DEVID 0x00000000
19 #define CS35L41_REVID 0x00000004
20 #define CS35L41_FABID 0x00000008
21 #define CS35L41_RELID 0x0000000C
22 #define CS35L41_OTPID 0x00000010
23 #define CS35L41_SFT_RESET 0x00000020
24 #define CS35L41_TEST_KEY_CTL 0x00000040
25 #define CS35L41_USER_KEY_CTL 0x00000044
[all …]
/linux/drivers/clk/bcm/
H A Dclk-bcm2835.c40 #define CM_PASSWORD 0x5a000000
42 #define CM_GNRICCTL 0x000
43 #define CM_GNRICDIV 0x004
45 # define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0)
47 #define CM_VPUCTL 0x008
48 #define CM_VPUDIV 0x00c
49 #define CM_SYSCTL 0x010
50 #define CM_SYSDIV 0x014
51 #define CM_PERIACTL 0x018
52 #define CM_PERIADIV 0x01c
[all …]
/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8822c_table.c16 0x83000000, 0x00000000, 0x40000000, 0x00000000,
17 0x1D90, 0x300001FF,
18 0x1D90, 0x300101FE,
19 0x1D90, 0x300201FD,
20 0x1D90, 0x300301FC,
21 0x1D90, 0x300401FB,
22 0x1D90, 0x300501FA,
23 0x1D90, 0x300601F9,
24 0x1D90, 0x300701F8,
25 0x1D90, 0x300801F7,
[all …]