Home
last modified time | relevance | path

Searched +full:0 +full:x58000000 (Results 1 – 25 of 49) sorted by relevance

12

/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8-ss-img.dtsi8 #clock-cells = <0>;
17 ranges = <0x58000000 0x0 0x58000000 0x1000000>;
20 reg = <0x58400000 0x00050000>;
32 reg = <0x58450000 0x00050000>;
45 reg = <0x585d0000 0x10000>;
57 reg = <0x585f0000 0x10000>;
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dfaraday,ftpci100.txt9 The host controller appear on the PCI bus with vendor ID 0x159b (Faraday
10 Technology) and product ID 0x4321.
23 - bus-range: set to <0x00 0xff>
45 - #address-cells: set to <0>
64 interrupt-map-mask = <0xf800 0 0 7>;
66 <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
67 <0x4800 0 0 2 &pci_intc 1>,
68 <0x4800 0 0 3 &pci_intc 2>,
69 <0x4800 0 0 4 &pci_intc 3>,
70 <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
[all …]
H A Dfaraday,ftpci100.yaml18 The host controller appear on the PCI bus with vendor ID 0x159b (Faraday
19 Technology) and product ID 0x4321.
34 interrupt-map-mask = <0xf800 0 0 7>;
36 <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
37 <0x4800 0 0 2 &pci_intc 1>,
38 <0x4800 0 0 3 &pci_intc 2>,
39 <0x4800 0 0 4 &pci_intc 3>,
40 <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
41 <0x5000 0 0 2 &pci_intc 2>,
42 <0x5000 0 0 3 &pci_intc 3>,
[all …]
H A Dnvidia,tegra20-pcie.txt27 - cell 0 specifies the bus and device numbers of the root port:
30 - cell 1 denotes the upper 32 address bits and should be 0
45 - 0x81000000: I/O memory region
46 - 0x82000000: non-prefetchable memory region
47 - 0xc2000000: prefetchable memory region
73 - pinctrl-0: phandle for the default/active state of pin configurations.
104 - If lanes 0 to 3 are used:
150 - Root port 0 uses 4 lanes, root port 1 is unused.
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
171 reg = <0x80003000 0x00000800 /* PADS registers */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/gpu/
H A Dnvidia,gk20a.txt46 reg = <0x0 0x57000000 0x0 0x01000000>,
47 <0x0 0x58000000 0x0 0x01000000>;
64 reg = <0x0 0x57000000 0x0 0x01000000>,
65 <0x0 0x58000000 0x0 0x01000000>;
82 reg = <0x0 0x17000000 0x0 0x1000000>,
83 <0x0 0x18000000 0x0 0x1000000>;
100 reg = <0x17000000 0x1000000>,
101 <0x18000000 0x1000000>;
/freebsd/sys/contrib/device-tree/src/arm/gemini/
H A Dgemini.dtsi23 pinctrl-0 = <&pflash_default_pins>;
31 reg = <0x40000000 0x1000>;
39 offset = <0x0c>;
41 mask = <0xC0000000>;
49 pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
159 reg = <0x41000000 0x1000>;
168 reg = <0x42000000 0x100>;
173 pinctrl-0 = <&uart_default_pins>;
179 reg = <0x43000000 0x1000>;
193 reg = <0x45000000 0x100>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dnvidia,tegra20-mc.txt15 - #iommu-cells: Should be 0. This cell represents the number of cells in an
25 reg = <0x7000f000 0x400 /* controller registers */
26 0x58000000 0x02000000>; /* GART aperture */
29 interrupts = <GIC_SPI 77 0x04>;
31 #iommu-cells = <0>;
H A Dnvidia,tegra20-mc.yaml48 const: 0
69 reg = <0x7000f000 0x400>, /* Controller registers */
70 <0x58000000 0x02000000>; /* GART aperture */
74 interrupts = <0 77 4>;
76 #iommu-cells = <0>;
/freebsd/tools/test/stress2/misc/
H A Djail.sh36 sed '1,/^EOF/d' < $odir/$0 > jail.c
54 j.path = (char *)0xa000000;
56 j.jailname = (char *)0;
57 j.ip4s = 0;
58 j.ip6s = 0;
59 j.ip4 = (struct in_addr *)0x58000000;
60 j.ip6 = (struct in6_addr *)0x33000001;
65 return (0);
/freebsd/lib/msun/ld80/
H A Ds_cospil.c41 pi_hi = 3.1415926814079285e+00, /* 0x400921fb 0x58000000 */
42 pi_lo =-2.7818135228334233e-08; /* 0xbe5dde97 0x3dcb3b3a */
47 volatile static const double vzero = 0;
58 ix = hx & 0x7fff; in cospil()
63 if (ix < 0x3fff) { /* |x| < 1 */ in cospil()
64 if (ix < 0x3ffd) { /* |x| < 0.25 */ in cospil()
65 if (ix < 0x3fdd) { /* |x| < 0x1p-34 */ in cospil()
66 if ((int)x == 0) in cospil()
72 if (ix < 0x3ffe) /* |x| < 0.5 */ in cospil()
74 else if (lx < 0xc000000000000000ull) { /* |x| < 0.75 */ in cospil()
[all …]
H A Ds_tanpil.c41 pi_hi = 3.1415926814079285e+00, /* 0x400921fb 0x58000000 */
42 pi_lo = -2.7818135228334233e-08; /* 0xbe5dde97 0x3dcb3b3a */
70 volatile static const double vzero = 0;
81 ix = hx & 0x7fff; in tanpil()
86 if (ix < 0x3fff) { /* |x| < 1 */ in tanpil()
87 if (ix < 0x3ffe) { /* |x| < 0.5 */ in tanpil()
88 if (ix < 0x3fdd) { /* |x| < 0x1p-34 */ in tanpil()
89 if (x == 0) in tanpil()
92 lx & 0xffffffff00000000ull); in tanpil()
93 hi *= 0x1p63L; in tanpil()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/ti/
H A Dti,omap-dss.txt50 reg = <0x58000000 0x80>;
61 reg = <0x58001000 0x1000>;
70 reg = <0x58006000 0x200>,
71 <0x58006200 0x100>,
72 <0x58006300 0x100>,
73 <0x58006400 0x1000>;
99 tfp410: encoder@0 {
101 gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; /* 0, power-down */
104 pinctrl-0 = <&tfp410_pins>;
108 #size-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/renesas/
H A Dr8a779f4-s4sk.dts37 reg = <0x0 0x48000000 0x0 0x58000000>;
42 reg = <0x4 0x80000000 0x0 0x80000000>;
68 pinctrl-0 = <&hscif0_pins>;
76 pinctrl-0 = <&hscif1_pins>;
84 pinctrl-0 = <&i2c2_pins>;
92 pinctrl-0 = <&i2c4_pins>;
100 pinctrl-0 = <&i2c5_pins>;
108 reg = <0x50>;
114 pinctrl-0 = <&sd_pins>;
124 pinctrl-0 = <&scif_clk_pins>;
[all …]
H A Dr9a09g011-v2mevk2.dts33 #size-cells = <0>;
35 port@0 {
36 reg = <0>;
57 reg = <0x0 0x58000000 0x0 0x28000000>;
62 reg = <0x1 0x80000000 0x0 0x80000000>;
90 gpios = <&pwc 0 GPIO_ACTIVE_HIGH>;
92 states = <3300000 0>, <1800000 1>;
102 phy0: ethernet-phy@0 {
105 reg = <0>;
110 pinctrl-0 = <&emmc_pins>;
[all …]
/freebsd/lib/msun/src/
H A De_j0f.c25 static const volatile float vone = 1, vzero = 0;
30 invsqrtpi= 5.6418961287e-01, /* 0x3f106ebb */
31 tpi = 6.3661974669e-01, /* 0x3f22f983 */
32 /* R0/S0 on [0, 2.00] */
33 R02 = 1.5625000000e-02, /* 0x3c800000 */
34 R03 = -1.8997929874e-04, /* 0xb947352e */
35 R04 = 1.8295404516e-06, /* 0x35f58e88 */
36 R05 = -4.6183270541e-09, /* 0xb19eaf3c */
37 S01 = 1.5619102865e-02, /* 0x3c7fe744 */
38 S02 = 1.1692678527e-04, /* 0x38f53697 */
[all …]
H A De_j1f.c25 static const volatile float vone = 1, vzero = 0;
30 invsqrtpi= 5.6418961287e-01, /* 0x3f106ebb */
31 tpi = 6.3661974669e-01, /* 0x3f22f983 */
32 /* R0/S0 on [0,2] */
33 r00 = -6.2500000000e-02, /* 0xbd800000 */
34 r01 = 1.4070566976e-03, /* 0x3ab86cfd */
35 r02 = -1.5995563444e-05, /* 0xb7862e36 */
36 r03 = 4.9672799207e-08, /* 0x335557d2 */
37 s01 = 1.9153760746e-02, /* 0x3c9ce859 */
38 s02 = 1.8594678841e-04, /* 0x3942fab6 */
[all …]
H A Ds_sinpi.c34 * threshold is |x| < 0x1pN with N = -(P/2+M). P is the precision of the
43 * 3. For 1 <= |x| < 0x1p(P-1), argument reduction is required where
45 * 0 <= r < 1. With the given domain, a simplified inline floor(x)
56 * 4. For |x| >= 0x1p(P-1), |x| is integral and sinpi(x) = copysign(0,x).
60 * sinpi(+-0) = +-0
61 * sinpi(+-n) = +-0, for positive integers n.
71 pi_hi = 3.1415926814079285e+00, /* 0x400921fb 0x58000000 */
72 pi_lo =-2.7818135228334233e-08; /* 0xbe5dde97 0x3dcb3b3a */
77 volatile static const double vzero = 0;
86 ix = hx & 0x7fffffff; in sinpi()
[all …]
H A Ds_cospi.c33 * threshold is used. The threshold is |x| < 0x1pN with N = -(P/2+M).
40 * 3. For 1 <= |x| < 0x1p(P-1), argument reduction is required where
42 * 0 <= r < 1. With the given domain, a simplified inline floor(x)
53 * 4. For |x| >= 0x1p(P-1), |x| is integral and cospi(x) = 1.
57 * cospi(+-0) = 1.
58 * cospi(n.5) = 0 for n an integer.
68 pi_hi = 3.1415926814079285e+00, /* 0x400921fb 0x58000000 */
69 pi_lo =-2.7818135228334233e-08; /* 0xbe5dde97 0x3dcb3b3a */
74 volatile static const double vzero = 0;
83 ix = hx & 0x7fffffff; in cospi()
[all …]
H A Ds_tanpi.c34 * threshold is |x| < 0x1pN with N = -(P/2+M). P is the precision of the
43 * 3. For 1 <= |x| < 0x1p(P-1), argument reduction is required where
45 * 0 <= r < 1. With the given domain, a simplified inline floor(x)
54 * 4. For |x| >= 0x1p(P-1), |x| is integral and tanpi(x) = copysign(0,x).
58 * tanpi(+-0) = +-0
59 * tanpi(n) = +0 for positive even and negative odd integer n.
60 * tanpi(n) = -0 for positive odd and negative even integer n.
75 pi_hi = 3.1415926814079285e+00, /* 0x400921fb 0x58000000 */
76 pi_lo = -2.7818135228334233e-08; /* 0xbe5dde97 0x3dcb3b3a */
108 volatile static const double vzero = 0;
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7915/
H A Dmmio.c21 [INT_SOURCE_CSR] = 0xd7010,
22 [INT_MASK_CSR] = 0xd7014,
23 [INT1_SOURCE_CSR] = 0xd7088,
24 [INT1_MASK_CSR] = 0xd708c,
25 [INT_MCU_CMD_SOURCE] = 0xd51f0,
26 [INT_MCU_CMD_EVENT] = 0x3108,
27 [WFDMA0_ADDR] = 0xd4000,
28 [WFDMA0_PCIE1_ADDR] = 0xd8000,
29 [WFDMA_EXT_CSR_ADDR] = 0xd7000,
30 [CBTOP1_PHY_END] = 0x77ffffff,
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap5.dtsi45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0>;
69 reg = <0x1>;
115 reg = <0 0x40300000 0 0x20000>; /* 128k */
122 reg = <0 0x48211000 0 0x1000>,
123 <0 0x48212000 0 0x2000>,
124 <0 0x48214000 0 0x2000>,
125 <0 0x48216000 0 0x2000>;
133 reg = <0 0x48281000 0 0x1000>;
[all …]
H A Domap4.dtsi40 #size-cells = <0>;
42 cpu@0 {
46 reg = <0x0>;
57 reg = <0x1>;
67 reg = <0x40304000 0xa000>; /* 40k */
74 reg = <0x48241000 0x1000>,
75 <0x48240100 0x0100>;
81 reg = <0x48242000 0x1000>;
89 reg = <0x48240600 0x20>;
98 reg = <0x48281000 0x1000>;
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7996/
H A Dmmio.c15 [WF_AGG_BASE] = { { 0x820e2000, 0x820f2000, 0x830e2000 } },
16 [WF_ARB_BASE] = { { 0x820e3000, 0x820f3000, 0x830e3000 } },
17 [WF_TMAC_BASE] = { { 0x820e4000, 0x820f4000, 0x830e4000 } },
18 [WF_RMAC_BASE] = { { 0x820e5000, 0x820f5000, 0x830e5000 } },
19 [WF_DMA_BASE] = { { 0x820e7000, 0x820f7000, 0x830e7000 } },
20 [WF_WTBLOFF_BASE] = { { 0x820e9000, 0x820f9000, 0x830e9000 } },
21 [WF_ETBF_BASE] = { { 0x820ea000, 0x820fa000, 0x830ea000 } },
22 [WF_LPON_BASE] = { { 0x820eb000, 0x820fb000, 0x830eb000 } },
23 [WF_MIB_BASE] = { { 0x820ed000, 0x820fd000, 0x830ed000 } },
24 [WF_RATE_BASE] = { { 0x820ee000, 0x820fe000, 0x830ee000 } },
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7921/
H A Dpci.c20 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7961),
22 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7922),
24 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0608),
26 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0616),
65 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ in __mt7921_reg_addr()
66 { 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ in __mt7921_reg_addr()
67 { 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ in __mt7921_reg_addr()
68 { 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ in __mt7921_reg_addr()
69 { 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */ in __mt7921_reg_addr()
70 { 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */ in __mt7921_reg_addr()
[all …]
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/LoongArch/
H A DEmulateInstructionLoongArch.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
39 {0xfc000000, 0x40000000, &EmulateInstructionLoongArch::EmulateBEQZ, in GetOpcodeForInstruction()
41 {0xfc000000, 0x44000000, &EmulateInstructionLoongArch::EmulateBNEZ, in GetOpcodeForInstruction()
43 {0xfc000300, 0x48000000, &EmulateInstructionLoongArch::EmulateBCEQZ, in GetOpcodeForInstruction()
45 {0xfc000300, 0x48000100, &EmulateInstructionLoongArch::EmulateBCNEZ, in GetOpcodeForInstruction()
47 {0xfc000000, 0x4c000000, &EmulateInstructionLoongArch::EmulateJIRL, in GetOpcodeForInstruction()
49 {0xfc000000, 0x50000000, &EmulateInstructionLoongArch::EmulateB, in GetOpcodeForInstruction()
51 {0xfc000000, 0x54000000, &EmulateInstructionLoongArch::EmulateBL, in GetOpcodeForInstruction()
53 {0xfc000000, 0x58000000, &EmulateInstructionLoongArch::EmulateBEQ, in GetOpcodeForInstruction()
55 {0xfc000000, 0x5c000000, &EmulateInstructionLoongArch::EmulateBNE, in GetOpcodeForInstruction()
[all …]

12