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/freebsd/sys/contrib/device-tree/Bindings/display/tegra/
H A Dnvidia,tegra20-host1x.yaml175 use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to
211 - description: host1x syncpoint interrupt 0
235 use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to
251 reg = <0x50000000 0x00024000>;
252 interrupts = <0 65 0x04>, /* mpcore syncpt */
253 <0 67 0x04>; /* mpcore general */
263 ranges = <0x54000000 0x54000000 0x04000000>;
267 reg = <0x54040000 0x00040000>;
268 interrupts = <0 68 0x04>;
276 reg = <0x54080000 0x00040000>;
[all …]
H A Dnvidia,tegra20-host1x.txt106 - reg: csi port number. Valid port numbers are 0 through 5.
120 port@0 with single child 'endpoint' node always a sink.
123 port@0 (required node)
125 - reg: 0
440 reg = <0x50000000 0x00024000>;
441 interrupts = <0 65 0x04 /* mpcore syncpt */
442 0 67 0x04>; /* mpcore general */
452 ranges = <0x54000000 0x54000000 0x04000000>;
456 reg = <0x54040000 0x00040000>;
457 interrupts = <0 68 0x04>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/intel/ixp/
H A Dintel-ixp4xx.dtsi19 * windows in the 256MB space from 0x50000000 to 0x5fffffff.
26 ranges = <0 0x0 0x50000000 0x01000000>,
27 <1 0x0 0x51000000 0x01000000>,
28 <2 0x0 0x52000000 0x01000000>,
29 <3 0x0 0x53000000 0x01000000>,
30 <4 0x0 0x54000000 0x01000000>,
31 <5 0x0 0x55000000 0x01000000>,
32 <6 0x0 0x56000000 0x01000000>,
33 <7 0x0 0x57000000 0x01000000>;
34 dma-ranges = <0 0x0 0x50000000 0x01000000>,
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/
H A Dmarvell,pxa300-gcu.txt14 reg = <0x54000000 0x1000>;
/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra30-asus-nexus7-tilapia-memory-timings.dtsi13 emc-timings-0 {
17 nvidia,emc-auto-cal-interval = <0x001fffff>;
18 nvidia,emc-mode-1 = <0x80100002>;
19 nvidia,emc-mode-2 = <0x80200018>;
20 nvidia,emc-mode-reset = <0x80000b71>;
21 nvidia,emc-zcal-cnt-long = <0x00000040>;
25 0x0000001f /* EMC_RC */
26 0x00000069 /* EMC_RFC */
27 0x00000017 /* EMC_RAS */
28 0x00000007 /* EMC_RP */
[all …]
H A Dtegra30-asus-tf300t.dts75 reg = <0x10>;
94 mount-matrix = "0", "-1", "0",
95 "-1", "0", "0",
96 "0", "0", "-1";
100 mount-matrix = "-1", "0", "0",
101 "0", "1", "0",
102 "0", "0", "-1";
107 mount-matrix = "0", "-1", "0",
108 "-1", "0", "0",
109 "0", "0", "1";
[all …]
H A Dtegra30-asus-tf300tg.dts22 <TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>,
171 reg = <0x10>;
190 mount-matrix = "1", "0", "0",
191 "0", "-1", "0",
192 "0", "0", "-1";
196 mount-matrix = "-1", "0", "0",
197 "0", "1", "0",
198 "0", "0", "-1";
203 mount-matrix = "0", "-1", "0",
204 "-1", "0", "0",
[all …]
H A Dtegra30-asus-tf700t.dts92 reg = <0x10>;
111 mount-matrix = "1", "0", "0",
112 "0", "-1", "0",
113 "0", "0", "-1";
117 mount-matrix = "0", "1", "0",
118 "1", "0", "
[all...]
H A Dtegra114.dtsi17 reg = <0x80000000 0x0>;
22 reg = <0x40000000 0x40000>;
25 ranges = <0 0x40000000 0x40000>;
28 reg = <0x400 0x3fc00>;
35 reg = <0x5000000
[all...]
H A Dtegra20.dtsi17 memory@0 {
19 reg = <0 0>;
24 reg = <0x40000000 0x40000>;
27 ranges = <0 0x40000000 0x40000>;
30 reg = <0x400 0x3fc0
[all...]
H A Dtegra124.dtsi21 reg = <0x0 0x80000000 0x0 0x0>;
27 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
28 <0x0 0x0100380
[all...]
H A Dtegra30.dtsi20 reg = <0x80000000 0x0>;
26 reg = <0x00003000 0x00000800>, /* PADS registers */
27 <0x00003800 0x00000200>, /* AFI registers */
28 <0x10000000 0x10000000>; /* configuration space */
35 interrupt-map-mask = <0 0
[all...]
H A Dtegra30-asus-nexus7-grouper-memory-timings.dtsi5 emc-timings-0 {
6 nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */
12 0x00020001 /* MC_EMEM_ARB_CFG */
13 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */
14 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
15 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
16 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
17 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
18 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
19 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
[all …]
/freebsd/contrib/opencsd/decoder/source/i_dec/
H A Dtrc_idec_arminst.cpp48 if ((inst & 0xf0000000) == 0xf0000000) { in inst_ARM_is_direct_branch()
50 if ((inst & 0xfe000000) == 0xfa000000){ in inst_ARM_is_direct_branch()
53 is_direct_branch = 0; in inst_ARM_is_direct_branch()
55 } else if ((inst & 0x0e000000) == 0x0a000000) { in inst_ARM_is_direct_branch()
58 is_direct_branch = 0; in inst_ARM_is_direct_branch()
65 if ( ((inst & 0xf0000000) != 0xf0000000) && in inst_ARM_wfiwfe()
66 ((inst & 0x0ffffffe) == 0x0320f002) in inst_ARM_wfiwfe()
70 return 0; in inst_ARM_wfiwfe()
76 if ((inst & 0xf0000000) == 0xf0000000) { in inst_ARM_is_indirect_branch()
78 if ((inst & 0xfe500000) == 0xf8100000) { in inst_ARM_is_indirect_branch()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dnvidia,tegra30-emc.yaml35 const: 0
53 "^emc-timings-[0-9]+$":
62 "^timing-[0-9]+$":
75 minimum: 0
91 Mode Register 0.
98 minimum: 0
239 reg = <0x7000f400 0x400>;
240 interrupts = <0 78 4>;
247 #interconnect-cells = <0>;
255 nvidia,emc-auto-cal-interval = <0x001fffff>;
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7915/
H A Dmmio.c21 [INT_SOURCE_CSR] = 0xd7010,
22 [INT_MASK_CSR] = 0xd7014,
23 [INT1_SOURCE_CSR] = 0xd7088,
24 [INT1_MASK_CSR] = 0xd708c,
25 [INT_MCU_CMD_SOURCE] = 0xd51f0,
26 [INT_MCU_CMD_EVENT] = 0x3108,
27 [WFDMA0_ADDR] = 0xd4000,
28 [WFDMA0_PCIE1_ADDR] = 0xd8000,
29 [WFDMA_EXT_CSR_ADDR] = 0xd7000,
30 [CBTOP1_PHY_END] = 0x77ffffff,
[all …]
/freebsd/sys/contrib/device-tree/src/arm/intel/pxa/
H A Dpxa3xx.dtsi6 ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \
7 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
8 (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) : \
9 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
10 0)
12 ((gpio <= 1) ? (0x674 + 4 * gpio) : \
13 (gpio <= 6) ? (0x2dc + 4 * gpio) : \
14 0)
17 ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \
18 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7996/
H A Dmmio.c24 [WF_AGG_BASE] = { { 0x820e2000, 0x820f2000, 0x830e2000 } },
25 [WF_ARB_BASE] = { { 0x820e3000, 0x820f3000, 0x830e3000 } },
26 [WF_TMAC_BASE] = { { 0x820e4000, 0x820f4000, 0x830e4000 } },
27 [WF_RMAC_BASE] = { { 0x820e5000, 0x820f5000, 0x830e5000 } },
28 [WF_DMA_BASE] = { { 0x820e7000, 0x820f7000, 0x830e7000 } },
29 [WF_WTBLOFF_BASE] = { { 0x820e9000, 0x820f9000, 0x830e9000 } },
30 [WF_ETBF_BASE] = { { 0x820ea000, 0x820fa000, 0x830ea000 } },
31 [WF_LPON_BASE] = { { 0x820eb000, 0x820fb000, 0x830eb000 } },
32 [WF_MIB_BASE] = { { 0x820ed000, 0x820fd000, 0x830ed000 } },
33 [WF_RATE_BASE] = { { 0x820ee000, 0x820fe000, 0x830ee000 } },
[all …]
/freebsd/sys/contrib/device-tree/src/riscv/canaan/
H A Dk210.dtsi27 #size-cells = <0>;
29 cpu0: cpu@0 {
32 reg = <0>;
36 i-cache-size = <0x8000>;
38 d-cache-size = <0x8000>;
52 i-cache-size = <0x8000>;
54 d-cache-size = <0x8000>;
77 reg = <0x80000000 0x400000>, /* sram0 4 MiB */
78 <0x80400000 0x200000>, /* sram1 2 MiB */
79 <0x80600000 0x200000>; /* aisram 2 MiB */
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra132.dtsi22 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
23 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
24 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
31 interrupt-map-mask = <0 0 0 0>;
32 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
34 bus-range = <0x00 0xff>;
38 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
39 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
40 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
41 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt792x_regs.h8 #define MT_MCU_WFDMA1_BASE 0x3000
11 #define MT_MCU_INT_EVENT MT_MCU_WFDMA1(0x108)
12 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)
17 #define MT_PLE_BASE 0x820c0000
20 #define MT_PLE_FL_Q0_CTRL MT_PLE(0x3e0)
21 #define MT_PLE_FL_Q1_CTRL MT_PLE(0x3e4)
22 #define MT_PLE_FL_Q2_CTRL MT_PLE(0x3e8)
23 #define MT_PLE_FL_Q3_CTRL MT_PLE(0x3ec)
25 #define MT_PLE_AC_QEMPTY(_n) MT_PLE(0x500 + 0x40 * (_n))
26 #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2))
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7921/
H A Dpci.c21 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7961),
23 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7922),
25 { PCI_DEVICE(PCI_VENDOR_ID_ITTIM, 0x7922),
27 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0608),
29 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0616),
31 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7920),
74 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ in __mt7921_reg_addr()
75 { 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ in __mt7921_reg_addr()
76 { 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ in __mt7921_reg_addr()
77 { 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ in __mt7921_reg_addr()
[all …]
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/LoongArch/
H A DEmulateInstructionLoongArch.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
39 {0xfc000000, 0x40000000, &EmulateInstructionLoongArch::EmulateBEQZ, in GetOpcodeForInstruction()
41 {0xfc000000, 0x44000000, &EmulateInstructionLoongArch::EmulateBNEZ, in GetOpcodeForInstruction()
43 {0xfc000300, 0x48000000, &EmulateInstructionLoongArch::EmulateBCEQZ, in GetOpcodeForInstruction()
45 {0xfc000300, 0x48000100, &EmulateInstructionLoongArch::EmulateBCNEZ, in GetOpcodeForInstruction()
47 {0xfc000000, 0x4c000000, &EmulateInstructionLoongArch::EmulateJIRL, in GetOpcodeForInstruction()
49 {0xfc000000, 0x50000000, &EmulateInstructionLoongArch::EmulateB, in GetOpcodeForInstruction()
51 {0xfc000000, 0x54000000, &EmulateInstructionLoongArch::EmulateBL, in GetOpcodeForInstruction()
53 {0xfc000000, 0x58000000, &EmulateInstructionLoongArch::EmulateBEQ, in GetOpcodeForInstruction()
55 {0xfc000000, 0x5c000000, &EmulateInstructionLoongArch::EmulateBNE, in GetOpcodeForInstruction()
[all …]
/freebsd/sys/arm/include/
H A Darmreg.h44 #define PSR_MODE 0x0000001f /* mode mask */
45 #define PSR_USR32_MODE 0x00000010
46 #define PSR_FIQ32_MODE 0x00000011
47 #define PSR_IRQ32_MODE 0x00000012
48 #define PSR_SVC32_MODE 0x00000013
49 #define PSR_MON32_MODE 0x00000016
50 #define PSR_ABT32_MODE 0x00000017
51 #define PSR_HYP32_MODE 0x0000001a
52 #define PSR_UND32_MODE 0x0000001b
53 #define PSR_SYS32_MODE 0x0000001
[all...]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7925/
H A Dpci.c14 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7925),
16 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0717),
61 dev->backup_l1 = 0; in mt7925_reg_remap_restore()
66 dev->backup_l2 = 0; in mt7925_reg_remap_restore()
107 { 0x830c0000, 0x000000, 0x0001000 }, /* WF_MCU_BUS_CR_REMAP */ in __mt7925_reg_addr()
108 { 0x54000000, 0x002000, 0x0001000 }, /* WFDMA PCIE0 MCU DMA0 */ in __mt7925_reg_addr()
109 { 0x55000000, 0x003000, 0x0001000 }, /* WFDMA PCIE0 MCU DMA1 */ in __mt7925_reg_addr()
110 { 0x56000000, 0x004000, 0x0001000 }, /* WFDMA reserved */ in __mt7925_reg_addr()
111 { 0x57000000, 0x005000, 0x0001000 }, /* WFDMA MCU wrap CR */ in __mt7925_reg_addr()
112 { 0x58000000, 0x006000, 0x0001000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */ in __mt7925_reg_addr()
[all …]

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