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/linux/drivers/clk/visconti/
H A Dclkc-tmpv770x.c43 { TMPV770X_CLK_PIPLL1_DIV4, "pipll1_div4", "pipll1", 0, 1, 4, },
45 { TMPV770X_CLK_PIPLL1_DIV2, "pipll1_div2", "pipll1", 0, 1, 2, },
47 { TMPV770X_CLK_PIPLL1_DIV1, "pipll1_div1", "pipll1", 0, 1, 1, },
50 { TMPV770X_CLK_PIDNNPLL_DIV1, "pidnnpll_div1", "pidnnpll", 0, 1, 1, },
51 { TMPV770X_CLK_PIREFCLK, "pirefclk", "osc2-clk", 0, 1, 1, },
52 { TMPV770X_CLK_WDTCLK, "wdtclk", "osc2-clk", 0, 1, 1, },
59 CLK_SET_RATE_PARENT, 0x34, 0x134, 4, 200,
63 CLK_SET_RATE_PARENT, 0x34, 0x134, 5, 20,
67 CLK_SET_RATE_PARENT, 0x34, 0x134, 6, 10,
71 CLK_SET_RATE_PARENT, 0x34, 0x134, 7, 4,
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6dl-pinfunc.h13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
H A Dimx51-pinfunc.h13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
[all …]
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
/linux/drivers/clk/renesas/
H A Dr9a07g043-cpg.c18 #define CPG_PL2SDHI_DSEL (0x218)
21 #define SEL_SDHI0 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 0, 2)
74 {0, 1},
78 {0, 0},
82 {0, 1},
87 {0, 0},
106 DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
151 mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),
153 mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),
167 0x514, 0, MSTOP(BUS_REG1, BIT(7))),
[all …]
H A Dr9a07g044-cpg.c19 #define CPG_PL2SDHI_DSEL (0x218)
22 #define SEL_SDHI0 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 0, 2)
81 {0, 1},
85 {0, 0},
89 {0, 1},
94 {0, 0},
128 {0, 0},
133 {0, 16},
137 {0, 0},
162 DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dpci_nrtr_regs.h22 #define mmPCI_NRTR_HBW_MAX_CRED 0x100
24 #define mmPCI_NRTR_LBW_MAX_CRED 0x120
26 #define mmPCI_NRTR_DBG_E_ARB 0x300
28 #define mmPCI_NRTR_DBG_W_ARB 0x304
30 #define mmPCI_NRTR_DBG_N_ARB 0x308
32 #define mmPCI_NRTR_DBG_S_ARB 0x30C
34 #define mmPCI_NRTR_DBG_L_ARB 0x310
36 #define mmPCI_NRTR_DBG_E_ARB_MAX 0x320
38 #define mmPCI_NRTR_DBG_W_ARB_MAX 0x324
40 #define mmPCI_NRTR_DBG_N_ARB_MAX 0x328
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dbrcm,brcmstb-usb-phy.yaml66 minimum: 0
72 minimum: 0
163 reg = <0xf0470200 0xb8>,
164 <0xf0471940 0x6c0>;
179 reg = <0x29f0200 0x200>,
180 <0x29c0880 0x30>,
181 <0x29cc100 0x534>,
182 <0x2808000 0x24>,
183 <0x2980080 0x8>;
189 brcm,ioc = <0x0>;
[all …]
/linux/arch/alpha/kernel/
H A Dsys_mikasa.c41 outw(mask, 0x536); in mikasa_update_irq_hw()
70 pld = (((~inw(0x534) & 0x0000ffffUL) << 16) in mikasa_device_interrupt()
71 | (((unsigned long) inb(0xa0)) << 8) in mikasa_device_interrupt()
72 | inb(0x20)); in mikasa_device_interrupt()
97 mikasa_update_irq_hw(0); in mikasa_init_irq()
113 * Summary @ 0x536:
115 * 0 Interrupt Line A from slot 0
116 * 1 Interrupt Line B from slot 0
117 * 2 Interrupt Line C from slot 0
118 * 3 Interrupt Line D from slot 0
[all …]
/linux/drivers/video/fbdev/
H A Dplatinumfb.h54 * F = 14.3MHz * c0 / (c1 & 0x1f) / (1 << (c1 >> 5))
55 * Newer ones use the values in clocksel[0], for which the formula
57 * F = 15MHz * c0 / ((c1 & 0x1f) + 2) / (1 << (c1 >> 5))
69 #define DIV2 0x20
70 #define DIV4 0x40
71 #define DIV8 0x60
72 #define DIV16 0x80
76 0x5c00,
78 { 0xffc, 4, 0, 0, 0, 0, 0x428, 0,
79 0, 0xb3, 0xd3, 0x12, 0x1a5, 0x23, 0x28, 0x2d,
[all …]
/linux/drivers/gpib/tnt4882/
H A Dmite.h14 #define PCI_VENDOR_ID_NATINST 0x1093
64 #define CHAN_OFFSET(x) (0x100 * (x))
66 /* DMA base for chan 0 is 0x500, chan 1 is 0x600 */
68 #define MITE_CHOR 0x500
81 #define CHOR_START BIT(0)
84 #define MITE_CHCR 0x504
102 #define CHCR_FIFO_ON 0
104 #define CHCR_NO_BURSTEN 0
106 #define CHCR_NFTP0 CHCR_NFTP(0)
113 #define CHCR_NETP0 CHCR_NETP(0)
[all …]
/linux/arch/arm64/boot/dts/broadcom/bcmbca/
H A Dbcm6856.dtsi18 #size-cells = <0>;
20 B53_0: cpu@0 {
23 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
61 #clock-cells = <0>;
67 #clock-cells = <0>;
81 ranges = <0x0 0x0 0x81000000 0x8000>;
87 reg = <0x1000 0x1000>, /* GICD */
88 <0x2000 0x2000>, /* GICC */
89 <0x4000 0x2000>, /* GICH */
[all …]
H A Dbcm6858.dtsi18 #size-cells = <0>;
20 B53_0: cpu@0 {
23 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
39 reg = <0x0 0x2>;
47 reg = <0x0 0x3>;
79 #clock-cells = <0>;
85 #clock-cells = <0>;
99 ranges = <0x0 0x0 0x81000000 0x8000>;
105 reg = <0x1000 0x1000>, /* GICD */
[all …]
H A Dbcm63158.dtsi19 #size-cells = <0>;
21 B53_0: cpu@0 {
24 reg = <0x0 0x0>;
32 reg = <0x0 0x1>;
40 reg = <0x0 0x2>;
48 reg = <0x0 0x3>;
81 #clock-cells = <0>;
87 #clock-cells = <0>;
95 #clock-cells = <0>;
109 ranges = <0x0 0x0 0x81000000 0x8000>;
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm6846.dtsi18 #size-cells = <0>;
20 CA7_0: cpu@0 {
23 reg = <0x0>;
31 reg = <0x1>;
62 #clock-cells = <0>;
68 #clock-cells = <0>;
82 ranges = <0 0x81000000 0x8000>;
89 reg = <0x1000 0x1000>,
90 <0x2000 0x2000>,
91 <0x4000 0x2000>,
[all …]
H A Dbcm6878.dtsi18 #size-cells = <0>;
20 CA7_0: cpu@0 {
23 reg = <0x0>;
31 reg = <0x1>;
62 #clock-cells = <0>;
68 #clock-cells = <0>;
76 #clock-cells = <0>;
90 ranges = <0 0x81000000 0x8000>;
96 reg = <0x1000 0x1000>,
97 <0x2000 0x2000>,
[all …]
H A Dbcm63178.dtsi18 #size-cells = <0>;
20 CA7_0: cpu@0 {
23 reg = <0x0>;
31 reg = <0x1>;
39 reg = <0x2>;
72 #clock-cells = <0>;
78 #clock-cells = <0>;
86 #clock-cells = <0>;
100 ranges = <0 0x81000000 0x8000>;
107 reg = <0x1000 0x1000>,
[all …]
H A Dbcm6855.dtsi18 #size-cells = <0>;
20 CA7_0: cpu@0 {
23 reg = <0x0>;
31 reg = <0x1>;
39 reg = <0x2>;
71 #clock-cells = <0>;
77 #clock-cells = <0>;
85 #clock-cells = <0>;
99 ranges = <0 0x81000000 0x8000>;
106 reg = <0x1000 0x1000>,
[all …]
/linux/arch/powerpc/platforms/44x/
H A Dfsp2.h6 #define DCRN_CMU_ADDR 0x00C /* Chip management unic addr */
7 #define DCRN_CMU_DATA 0x00D /* Chip management unic data */
10 #define DCRN_PLB4_PCBI 0x010 /* PLB Crossbar ID/Rev Register */
11 #define DCRN_PLB4_P0ACR 0x011 /* PLB0 Arbiter Control Register */
12 #define DCRN_PLB4_P0ESRL 0x012 /* PLB0 Error Status Register Low */
13 #define DCRN_PLB4_P0ESRH 0x013 /* PLB0 Error Status Register High */
14 #define DCRN_PLB4_P0EARL 0x014 /* PLB0 Error Address Register Low */
15 #define DCRN_PLB4_P0EARH 0x015 /* PLB0 Error Address Register High */
16 #define DCRN_PLB4_P0ESRLS 0x016 /* PLB0 Error Status Register Low Set*/
17 #define DCRN_PLB4_P0ESRHS 0x017 /* PLB0 Error Status Register High */
[all …]
/linux/drivers/net/ethernet/aquantia/atlantic/hw_atl/
H A Dhw_atl_utils.c20 #define HW_ATL_UCP_0X370_REG 0x0370U
22 #define HW_ATL_MIF_CMD 0x0200U
23 #define HW_ATL_MIF_ADDR 0x0208U
24 #define HW_ATL_MIF_VAL 0x020CU
26 #define HW_ATL_MPI_RPC_ADDR 0x0334U
27 #define HW_ATL_RPC_CONTROL_ADR 0x0338U
28 #define HW_ATL_RPC_STATE_ADR 0x033CU
30 #define HW_ATL_MPI_FW_VERSION 0x18
31 #define HW_ATL_MPI_CONTROL_ADR 0x0368U
32 #define HW_ATL_MPI_STATE_ADR 0x036CU
[all …]
/linux/include/linux/mfd/mt6359/
H A Dregisters.h10 #define MT6359_SWCID 0xa
11 #define MT6359_TOPSTATUS 0x2a
12 #define MT6359_TOP_RST_MISC 0x14c
13 #define MT6359_MISC_TOP_INT_CON0 0x188
14 #define MT6359_MISC_TOP_INT_STATUS0 0x194
15 #define MT6359_TOP_INT_STATUS0 0x19e
16 #define MT6359_SCK_TOP_INT_CON0 0x528
17 #define MT6359_SCK_TOP_INT_STATUS0 0x534
18 #define MT6359_EOSC_CALI_CON0 0x53a
19 #define MT6359_EOSC_CALI_CON1 0x53c
[all …]
/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dsmu74_discrete.h37 #define POSTDIV_DIV_BY_1 0
400 #define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG)
762 #define SMU7_SCLK_CAC 0x561
763 #define SMU7_MCLK_CAC 0xF9
764 #define SMU7_VCLK_CAC 0x2DE
765 #define SMU7_DCLK_CAC 0x2DE
766 #define SMU7_ECLK_CAC 0x25E
767 #define SMU7_ACLK_CAC 0x25E
768 #define SMU7_SAMCLK_CAC 0x25E
769 #define SMU7_DISPCLK_CAC 0x100
[all …]
H A Dsmu73_discrete.h125 uint8_t PcieGenSpeed; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3
385 #define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG)
748 #define SMU7_SCLK_CAC 0x561
749 #define SMU7_MCLK_CAC 0xF9
750 #define SMU7_VCLK_CAC 0x2DE
751 #define SMU7_DCLK_CAC 0x2DE
752 #define SMU7_ECLK_CAC 0x25E
753 #define SMU7_ACLK_CAC 0x25E
754 #define SMU7_SAMCLK_CAC 0x25E
755 #define SMU7_DISPCLK_CAC 0x100
[all …]
/linux/include/linux/bcma/
H A Dbcma.h62 #define BCMA_MANUF_ARM 0x43B
63 #define BCMA_MANUF_MIPS 0x4A7
64 #define BCMA_MANUF_BCM 0x4BF
67 #define BCMA_CL_SIM 0x0
68 #define BCMA_CL_EROM 0x1
69 #define BCMA_CL_CORESIGHT 0x9
70 #define BCMA_CL_VERIF 0xB
71 #define BCMA_CL_OPTIMO 0xD
72 #define BCMA_CL_GEN 0xE
73 #define BCMA_CL_PRIMECELL 0xF
[all …]

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