| /linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/ |
| H A D | gaudi2_blocks_linux_driver.h | 16 #define mmDCORE0_TPC0_ROM_TABLE_BASE 0x0ull
17 #define DCORE0_TPC0_ROM_TABLE_MAX_OFFSET 0x1000
18 #define DCORE0_TPC0_ROM_TABLE_SECTION 0x1000
19 #define mmDCORE0_TPC0_EML_SPMU_BASE 0x1000ull
20 #define DCORE0_TPC0_EML_SPMU_MAX_OFFSET 0x1000
21 #define DCORE0_TPC0_EML_SPMU_SECTION 0x1000
22 #define mmDCORE0_TPC0_EML_ETF_BASE 0x2000ull
23 #define DCORE0_TPC0_EML_ETF_MAX_OFFSET 0x1000
24 #define DCORE0_TPC0_EML_ETF_SECTION 0x1000
25 #define mmDCORE0_TPC0_EML_STM_BASE 0x3000ull
[all …]
|
| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | v3-v360epc-pci.txt | 18 each be exactly 256MB (0x10000000) in size.
38 reg = <0x62000000 0x10000>, <0x61000000 0x01000000>;
42 bus-range = <0x00 0xff>;
43 ranges = 0x01000000 0 0x00000000 /* I/O space @00000000 */
44 0x60000000 0 0x01000000 /* 16 MiB @ LB 60000000 */
45 0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */
46 0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */
47 0x42000000 0 0x50000000 /* prefetchable memory @50000000 */
48 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */
49 dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */
[all …]
|
| /linux/Documentation/devicetree/bindings/tpm/ |
| H A D | tcg,tpm-tis-mmio.yaml | 31 at least 0x5000 bytes
46 reg = <0x90000 0x5000>;
|
| /linux/Documentation/devicetree/bindings/powerpc/fsl/ |
| H A D | pamu.txt | 12 "fsl,pamu-v1.0". The second is "fsl,pamu".
18 PAMU v1.0, on an SOC that has five PAMU devices, the size
19 is 0x5000.
56 For PAMU v1.0, this size is 0x1000.
95 compatible = "fsl,pamu-v1.0", "fsl,pamu";
96 reg = <0x20000 0x5000>;
97 ranges = <0 0x20000 0x5000>;
98 fsl,portid-mapping = <0xf80000>;
102 24 2 0 0
105 pamu0: pamu@0 {
[all …]
|
| /linux/arch/arm/boot/dts/arm/ |
| H A D | integratorap.dts | 17 #size-cells = <0>;
19 cpu@0 {
28 reg = <0>;
37 operating-points = <71000 0
38 66000 0
39 60000 0
40 48000 0
41 36000 0
42 24000 0
43 12000 0>;
[all …]
|
| /linux/drivers/of/unittest-data/ |
| H A D | tests-interrupts.dtsi | 26 #address-cells = <0>;
50 interrupt-map = <0x5000 1 2 &test_intc0 15>;
64 reg = <0x5000 0x100>;
|
| /linux/drivers/net/ethernet/dec/tulip/ |
| H A D | 21142.c | 21 static u16 t21142_csr13[] = { 0x0001, 0x0009, 0x0009, 0x0000, 0x0001, };
22 u16 t21142_csr14[] = { 0xFFFF, 0x0705, 0x0705, 0x0000, 0x7F3D, };
23 static u16 t21142_csr15[] = { 0x0008, 0x0006, 0x000E, 0x0008, 0x0008, };
36 int new_csr6 = 0; in t21142_media_task()
40 if ((csr14 & 0x80) && (csr12 & 0x7000) != 0x5000) in t21142_media_task()
46 if (tulip_check_duplex(dev) < 0) { in t21142_media_task()
70 } else if ((csr12 & 0x7000) != 0x5000) { in t21142_media_task()
77 new_csr6 = 0x82420000; in t21142_media_task()
78 dev->if_port = 0; in t21142_media_task()
79 iowrite32(0, ioaddr + CSR13); in t21142_media_task()
[all …]
|
| /linux/include/linux/mdio/ |
| H A D | mdio-xgene.h | 15 #define BLOCK_XG_MDIO_CSR_OFFSET 0x5000
16 #define BLOCK_DIAG_CSR_OFFSET 0xd000
17 #define XGENET_CONFIG_REG_ADDR 0x20
19 #define MAC_ADDR_REG_OFFSET 0x00
20 #define MAC_COMMAND_REG_OFFSET 0x04
21 #define MAC_WRITE_REG_OFFSET 0x08
22 #define MAC_READ_REG_OFFSET 0x0c
23 #define MAC_COMMAND_DONE_REG_OFFSET 0x10
25 #define CLKEN_OFFSET 0x08
26 #define SRST_OFFSET 0x00
[all …]
|
| /linux/arch/powerpc/platforms/52xx/ |
| H A D | mpc52xx_sleep.S | 14 ori r7, r7, 0x8000 /* EE */
18 li r10, 0 /* flag that irq handler sets */
21 lwz r8, 0x14(r6) /* intr->main_mask */
22 ori r8, r8, 0x1
23 xori r8, r8, 0x1
24 stw r8, 0x14(r6)
28 li r8, 0x1
29 stw r8, 0x40(r6) /* intr->main_emulate */
39 ori r10, r10, 0x2000
55 ori r10, r10, 0x2000
[all …]
|
| /linux/arch/arm/boot/dts/gemini/ |
| H A D | gemini.dtsi | 23 pinctrl-0 = <&pflash_default_pins>;
31 reg = <0x40000000 0x1000>;
39 offset = <0x0c>;
41 mask = <0xC0000000>;
49 pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
159 reg = <0x41000000 0x1000>;
168 reg = <0x42000000 0x100>;
173 pinctrl-0 = <&uart_default_pins>;
179 reg = <0x43000000 0x1000>;
193 reg = <0x45000000 0x100>;
[all …]
|
| /linux/drivers/net/dsa/mv88e6xxx/ |
| H A D | global1.h | 16 /* Offset 0x00: Switch Global Status Register */
17 #define MV88E6XXX_G1_STS 0x00
18 #define MV88E6352_G1_STS_PPU_STATE 0x8000
19 #define MV88E6185_G1_STS_PPU_STATE_MASK 0xc000
20 #define MV88E6185_G1_STS_PPU_STATE_DISABLED_RST 0x0000
21 #define MV88E6185_G1_STS_PPU_STATE_INITIALIZING 0x4000
22 #define MV88E6185_G1_STS_PPU_STATE_DISABLED 0x8000
23 #define MV88E6185_G1_STS_PPU_STATE_POLLING 0xc000
24 #define MV88E6XXX_G1_STS_INIT_READY 0x0800
34 #define MV88E6XXX_G1_STS_IRQ_EEPROM_DONE 0
[all …]
|
| /linux/Documentation/devicetree/bindings/arm/ |
| H A D | arm,cci-400.yaml | 24 pattern: "^cci(@[0-9a-f]+)?$"
43 "^slave-if@[0-9a-f]+$":
65 "^pmu@[0-9a-f]+$":
119 arm,hbi = <0x249>;
129 * registers sits at address 0x000000002c090000.
131 * CCI slave interface @0x000000002c091000 is connected to dma
134 * CCI slave interface @0x000000002c094000 is connected to CPUs
137 * CCI slave interface @0x000000002c095000 is connected to CPUs
142 #size-cells = <0>;
145 CPU0: cpu@0 {
[all …]
|
| /linux/Documentation/devicetree/bindings/ata/ |
| H A D | marvell.txt | 11 - phy-names : Should be "0", "1", etc, one number per phandle
17 reg = <0x80000 0x5000>;
20 phy-names = "0", "1";
|
| /linux/drivers/net/ethernet/netronome/nfp/nfpcore/ |
| H A D | nfp_dev.h | 9 #define PCI_VENDOR_ID_CORIGINE 0x1da8
10 #define PCI_DEVICE_ID_NFP3800 0x3800
11 #define PCI_DEVICE_ID_NFP4000 0x4000
12 #define PCI_DEVICE_ID_NFP5000 0x5000
13 #define PCI_DEVICE_ID_NFP6000 0x6000
14 #define PCI_DEVICE_ID_NFP3800_VF 0x3803
15 #define PCI_DEVICE_ID_NFP6000_VF 0x6003
|
| /linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | mediatek,mt7621-memc.yaml | 31 reg = <0x5000 0x1000>;
|
| /linux/include/linux/qed/ |
| H A D | iwarp_common.h | 16 #define IWARP_ACTIVE_MODE 0
19 #define IWARP_SHARED_QUEUE_PAGE_SIZE (0x8000)
20 #define IWARP_SHARED_QUEUE_PAGE_RQ_PBL_OFFSET (0x4000)
21 #define IWARP_SHARED_QUEUE_PAGE_RQ_PBL_MAX_SIZE (0x1000)
22 #define IWARP_SHARED_QUEUE_PAGE_SQ_PBL_OFFSET (0x5000)
23 #define IWARP_SHARED_QUEUE_PAGE_SQ_PBL_MAX_SIZE (0x3000)
|
| /linux/include/uapi/linux/ |
| H A D | bpqether.h | 11 #define SIOCSBPQETHOPT (SIOCDEVPRIVATE+0) /* reserved */
25 #define SIOCGBPQETHPARAM 0x5000 /* get Level 1 parameters */
26 #define SIOCSBPQETHPARAM 0x5001 /* set */
|
| /linux/drivers/bus/ |
| H A D | omap_l3_smx.h | 14 #define L3_COMPONENT 0x000
15 #define L3_CORE 0x018
16 #define L3_AGENT_CONTROL 0x020
17 #define L3_AGENT_STATUS 0x028
18 #define L3_ERROR_LOG 0x058
23 #define L3_ERROR_LOG_ADDR 0x060
26 #define L3_SI_CONTROL 0x020
27 #define L3_SI_FLAG_STATUS_0 0x510
31 #define L3_STATUS_0_MPUIA_BRST (shift << 0)
95 #define L3_SI_FLAG_STATUS_1 0x530
[all …]
|
| /linux/drivers/gpu/drm/xe/ |
| H A D | xe_vm_doc.h | 56 * bind BO0 0x0-0x1000
57 * alloc page level 3a, program PTE[0] to BO0 phys address (CPU)
58 * alloc page level 2, program PDE[0] page level 3a phys address (CPU)
59 * alloc page level 1, program PDE[0] page level 2 phys address (CPU)
60 * update root PDE[0] to page level 1 phys address (GPU)
62 * bind BO1 0x201000-0x202000
66 * bind BO2 0x1ff000-0x201000
68 * update page level 3b PTE[0] to BO2 phys addres + 0x1000 (GPU)
157 * 0x0000-0x2000 and 0x3000-0x5000 have mappings
158 * Munmap 0x1000-0x4000, results in mappings 0x0000-0x1000 and 0x4000-0x5000
[all …]
|
| /linux/drivers/clk/qcom/ |
| H A D | gpucc-sm8250.c | 22 #define CX_GMU_CBCR_SLEEP_MASK 0xf
24 #define CX_GMU_CBCR_WAKE_MASK 0xf
36 { 249600000, 2000000000, 0 },
40 .l = 0x1a,
41 .alpha = 0xaaa,
42 .config_ctl_val = 0x20485699,
43 .config_ctl_hi_val = 0x00002261,
44 .config_ctl_hi1_val = 0x029a699c,
45 .user_ctl_val = 0x00000000,
46 .user_ctl_hi_val = 0x00000805,
[all …]
|
| /linux/arch/arc/boot/dts/ |
| H A D | vdk_axc003.dtsi | 22 ranges = <0x00000000 0xf0000000 0x10000000>;
25 #clock-cells = <0>;
38 reg = <0x5000 0x100>;
52 reg = < 0xe0012000 0x200 >;
61 ranges = <0x00000000 0x80000000 0x40000000>;
63 reg = <0x80000000 0x20000000>; /* 512MiB */
|
| /linux/drivers/staging/media/atomisp/i2c/ |
| H A D | ov2722.h | 38 #define I2C_MSG_LENGTH 0x2
47 * bits 31-16: numerator, bits 15-0: denominator
49 #define OV2722_FOCAL_LENGTH_DEFAULT 0x1160064
53 * bits 31-16: numerator, bits 15-0: denominator
55 #define OV2722_F_NUMBER_DEFAULT 0x1a000a
62 * bits 7-0: min f-number denominator
64 #define OV2722_F_NUMBER_RANGE 0x1a0a1a0a
65 #define OV2720_ID 0x2720
66 #define OV2722_ID 0x2722
68 #define OV2722_FINE_INTG_TIME_MIN 0
[all …]
|
| /linux/drivers/dma/ti/ |
| H A D | k3-psil-am62p.c | 83 PSIL_SAUL(0x7504, 20, 35, 8, 35, 0),
84 PSIL_SAUL(0x7505, 21, 35, 8, 36, 0),
85 PSIL_SAUL(0x7506, 22, 43, 8, 43, 0),
86 PSIL_SAUL(0x7507, 23, 43, 8, 44, 0),
88 PSIL_PDMA_XY_PKT(0x4300),
89 PSIL_PDMA_XY_PKT(0x4301),
90 PSIL_PDMA_XY_PKT(0x4302),
91 PSIL_PDMA_XY_PKT(0x4303),
92 PSIL_PDMA_XY_PKT(0x4304),
93 PSIL_PDMA_XY_PKT(0x4305),
[all …]
|
| /linux/arch/arm64/boot/dts/qcom/ |
| H A D | sc7280-herobrine-lte-sku.dtsi | 12 reg = <0x0 0x9c700000 0x0 0x200000>;
17 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
18 size = <0x0 0x4000>;
31 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>;
41 iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>;
42 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
51 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x8000 0x13000>;
52 qcom,ext-regs = <&tcsr_2 0x10000 0x10004 &tcsr_1 0x6004 0x6008>;
53 qcom,qaccept-regs = <&tcsr_1 0x3030 0x3040 0x3020>;
60 reg = <0x0 0x9c900000 0x0 0x800000>;
|
| /linux/drivers/media/i2c/ |
| H A D | ov13b10.c | 19 #define OV13B10_REG_MODE_SELECT 0x0100
20 #define OV13B10_MODE_STANDBY 0x00
21 #define OV13B10_MODE_STREAMING 0x01
23 #define OV13B10_REG_SOFTWARE_RST 0x0103
24 #define OV13B10_SOFTWARE_RST 0x01
27 #define OV13B10_REG_CHIP_ID 0x300a
28 #define OV13B10_CHIP_ID 0x560d42
31 #define OV13B10_REG_VTS 0x380e
32 #define OV13B10_VTS_30FPS 0x0c7c
33 #define OV13B10_VTS_60FPS 0x063e
[all …]
|