Lines Matching +full:0 +full:x5000

22 #define CX_GMU_CBCR_SLEEP_MASK		0xf
24 #define CX_GMU_CBCR_WAKE_MASK		0xf
36 	{ 249600000, 2000000000, 0 },
40 	.l = 0x1a,
41 	.alpha = 0xaaa,
42 	.config_ctl_val = 0x20485699,
43 	.config_ctl_hi_val = 0x00002261,
44 	.config_ctl_hi1_val = 0x029a699c,
45 	.user_ctl_val = 0x00000000,
46 	.user_ctl_hi_val = 0x00000805,
47 	.user_ctl_hi1_val = 0x00000000,
51 	.offset = 0x100,
68 	{ P_BI_TCXO, 0 },
82 	F(19200000, P_BI_TCXO, 1, 0, 0),
83 	F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
84 	F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
89 	.cmd_rcgr = 0x1120,
90 	.mnd_width = 0,
104 	.halt_reg = 0x1078,
107 		.enable_reg = 0x1078,
108 		.enable_mask = BIT(0),
117 	.halt_reg = 0x107c,
120 		.enable_reg = 0x107c,
121 		.enable_mask = BIT(0),
130 	.halt_reg = 0x1088,
133 		.enable_reg = 0x1088,
134 		.enable_mask = BIT(0),
143 	.halt_reg = 0x1098,
146 		.enable_reg = 0x1098,
147 		.enable_mask = BIT(0),
161 	.halt_reg = 0x108c,
164 		.enable_reg = 0x108c,
165 		.enable_mask = BIT(0),
174 	.halt_reg = 0x1004,
177 		.enable_reg = 0x1004,
178 		.enable_mask = BIT(0),
187 	.halt_reg = 0x109c,
190 		.enable_reg = 0x109c,
191 		.enable_mask = BIT(0),
200 	.halt_reg = 0x1064,
203 		.enable_reg = 0x1064,
204 		.enable_mask = BIT(0),
218 	.halt_reg = 0x5000,
221 		.enable_reg = 0x5000,
222 		.enable_mask = BIT(0),
231 	.gdscr = 0x106c,
232 	.gds_hw_ctrl = 0x1540,
241 	.gdscr = 0x100c,
242 	.clamp_io_ctrl = 0x1508,
266 	[GPUCC_GPU_CC_ACD_BCR] = { 0x1160 },
267 	[GPUCC_GPU_CC_CX_BCR] = { 0x1068 },
268 	[GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x10a0 },
269 	[GPUCC_GPU_CC_GMU_BCR] = { 0x111c },
270 	[GPUCC_GPU_CC_GX_BCR] = { 0x1008 },
271 	[GPUCC_GPU_CC_XO_BCR] = { 0x1000 },
283 	.max_register = 0x8008,
320 	value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT;  in gpu_cc_sm8250_probe()
321 	regmap_update_bits(regmap, 0x1098, mask, value);  in gpu_cc_sm8250_probe()