/linux/arch/s390/boot/ |
H A D | ipl_data.c | 15 psw_t32 ipl_psw; /* 0x0000 */ 16 struct ccw0 ccwpgm[2]; /* 0x0008 */ 17 u8 fill[56]; /* 0x0018 */ 18 struct ccw0 ccwpgmcc[20]; /* 0x0050 */ 19 u8 pad_0xf0[0x01a0-0x00f0]; /* 0x00f0 */ 20 psw_t restart_psw; /* 0x01a0 */ 21 psw_t external_new_psw; /* 0x01b0 */ 22 psw_t svc_new_psw; /* 0x01c0 */ 23 psw_t program_new_psw; /* 0x01d0 */ 24 psw_t mcck_new_psw; /* 0x01e0 */ [all …]
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/linux/drivers/media/dvb-frontends/ |
H A D | mb86a20s.c | 18 MB86A20S_13SEG = 0, 25 0xb0, 0xc0, 0xd0, 0xe0, 26 0xf0, 0x00, 0x10, 0x20, 59 { 0x70, 0x0f }, 60 { 0x70, 0xff }, 61 { 0x08, 0x01 }, 62 { 0x50, 0xd1 }, { 0x51, 0x20 }, 66 { 0x50, 0xd1 }, { 0x51, 0x22 }, 67 { 0x39, 0x01 }, 68 { 0x71, 0x00 }, [all …]
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/linux/Documentation/ABI/testing/ |
H A D | debugfs-iio-backend | 13 Reading address 0x50 14 echo 0x50 > direct_reg_access 17 Writing address 0x50 18 echo 0x50 0x3 > direct_reg_access 19 //readback address 0x50
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/linux/drivers/pinctrl/mediatek/ |
H A D | pinctrl-mt7981.c | 12 MTK_PIN(_number, _name, 0, _number, DRV_GRP4) 16 _x_bits, 32, 0) 23 PIN_FIELD(0, 56, 0x300, 0x10, 0, 4), 27 PIN_FIELD(0, 56, 0x0, 0x10, 0, 1), 31 PIN_FIELD(0, 56, 0x200, 0x10, 0, 1), 35 PIN_FIELD(0, 56, 0x100, 0x10, 0, 1), 39 PIN_FIELD_BASE(0, 0, 1, 0x10, 0x10, 1, 1), 40 PIN_FIELD_BASE(1, 1, 1, 0x10, 0x10, 0, 1), 41 PIN_FIELD_BASE(2, 2, 5, 0x20, 0x10, 6, 1), 42 PIN_FIELD_BASE(3, 3, 4, 0x20, 0x10, 6, 1), [all …]
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H A D | pinctrl-mt7986.c | 11 #define MT7986_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4) 17 _x_bits, 32, 0) 23 * iocfg_rt:0x11c30000, iocfg_rb:0x11c40000, iocfg_lt:0x11e20000, 24 * iocfg_lb:0x11e30000, iocfg_tr:0x11f00000, iocfg_tl:0x11f10000, 76 PIN_FIELD(0, 100, 0x300, 0x10, 0, 4), 80 PIN_FIELD(0, 100, 0x0, 0x10, 0, 1), 84 PIN_FIELD(0, 100, 0x200, 0x10, 0, 1), 88 PIN_FIELD(0, 100, 0x100, 0x10, 0, 1), 92 PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x40, 0x10, 17, 1), 93 PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x20, 0x10, 10, 1), [all …]
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H A D | pinctrl-mt8135.c | 17 #define DRV_BASE1 0x500 18 #define DRV_BASE2 0x510 19 #define PUPD_BASE1 0x400 20 #define PUPD_BASE2 0x450 21 #define R0_BASE1 0x4d0 22 #define R1_BASE1 0x200 23 #define R1_BASE2 0x250 49 MTK_DRV_GRP(2, 16, 0, 2, 2), 53 MTK_DRV_GRP(2, 8, 0, 1, 2), 55 MTK_DRV_GRP(4, 32, 0, 2, 4) [all …]
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H A D | pinctrl-mt8173.c | 18 #define DRV_BASE 0xb00 21 MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 2, 1, 0), /* KROW0 */ 22 MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 6, 5, 4), /* KROW1 */ 23 MTK_PIN_PUPD_SPEC_SR(121, 0xe00, 10, 9, 8), /* KROW2 */ 24 MTK_PIN_PUPD_SPEC_SR(122, 0xe10, 2, 1, 0), /* KCOL0 */ 25 MTK_PIN_PUPD_SPEC_SR(123, 0xe10, 6, 5, 4), /* KCOL1 */ 26 MTK_PIN_PUPD_SPEC_SR(124, 0xe10, 10, 9, 8), /* KCOL2 */ 28 MTK_PIN_PUPD_SPEC_SR(67, 0xd10, 2, 1, 0), /* ms0 DS */ 29 MTK_PIN_PUPD_SPEC_SR(68, 0xd00, 2, 1, 0), /* ms0 RST */ 30 MTK_PIN_PUPD_SPEC_SR(66, 0xc10, 2, 1, 0), /* ms0 cmd */ [all …]
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/linux/drivers/gpu/drm/panel/ |
H A D | panel-novatek-nt36672a.c | 89 for (i = 0; i < num; i++) { in nt36672a_send_cmds() 92 err = mipi_dsi_dcs_write(pinfo->link, cmd->data[0], cmd->data + 1, 1); in nt36672a_send_cmds() 94 if (err < 0) in nt36672a_send_cmds() 98 return 0; in nt36672a_send_cmds() 104 int ret = 0; in nt36672a_panel_power_off() 124 if (ret < 0) in nt36672a_panel_unprepare() 128 if (ret < 0) in nt36672a_panel_unprepare() 135 if (ret < 0) in nt36672a_panel_unprepare() 138 /* 0x3C = 60ms delay */ in nt36672a_panel_unprepare() 142 if (ret < 0) in nt36672a_panel_unprepare() [all …]
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H A D | panel-boe-tv101wum-ll2.c | 36 gpiod_set_value_cansleep(ctx->reset_gpio, 0); in boe_tv101wum_ll2_reset() 40 gpiod_set_value_cansleep(ctx->reset_gpio, 0); in boe_tv101wum_ll2_reset() 56 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x5a, 0x0e); in boe_tv101wum_ll2_on() 57 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0xff, 0x81, 0x68, 0x6c, 0x22, in boe_tv101wum_ll2_on() 58 0x6d, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00); in boe_tv101wum_ll2_on() 59 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x5a, 0x23); in boe_tv101wum_ll2_on() 60 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x90, 0x00, 0x00); in boe_tv101wum_ll2_on() 61 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x94, 0x2c, 0x00); in boe_tv101wum_ll2_on() 62 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x5a, 0x19); in boe_tv101wum_ll2_on() 63 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xa2, 0x38); in boe_tv101wum_ll2_on() [all …]
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/linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
H A D | dp.h | 12 #define DPCD_RC00_DPCD_REV 0x00000 13 #define DPCD_RC01_MAX_LINK_RATE 0x00001 14 #define DPCD_RC02 0x00002 15 #define DPCD_RC02_ENHANCED_FRAME_CAP 0x80 16 #define DPCD_RC02_TPS3_SUPPORTED 0x40 17 #define DPCD_RC02_MAX_LANE_COUNT 0x1f 18 #define DPCD_RC03 0x00003 19 #define DPCD_RC03_TPS4_SUPPORTED 0x80 20 #define DPCD_RC03_MAX_DOWNSPREAD 0x01 21 #define DPCD_RC0E 0x0000e [all …]
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/linux/drivers/media/tuners/ |
H A D | fc2580_priv.h | 23 {0x00, 0x00}, 24 {0x12, 0x86}, 25 {0x14, 0x5c}, 26 {0x16, 0x3c}, 27 {0x1f, 0xd2}, 28 {0x09, 0xd7}, 29 {0x0b, 0xd5}, 30 {0x0c, 0x32}, 31 {0x0e, 0x43}, 32 {0x21, 0x0a}, [all …]
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/linux/Documentation/firmware-guide/acpi/ |
H A D | i2c-muxes.rst | 13 | SMB1 |-->| MUX0 |--CH00--> i2c client A (0x50) 14 | | | 0x70 |--CH01--> i2c client B (0x50) 26 I2cSerialBus (0x70, ControllerInitiated, I2C_SPEED, 27 AddressingMode7Bit, "^SMB1", 0x00, 33 Name (_ADR, 0) 39 I2cSerialBus (0x50, ControllerInitiated, I2C_SPEED, 40 AddressingMode7Bit, "^CH00", 0x00, 54 I2cSerialBus (0x50, ControllerInitiated, I2C_SPEED, 55 AddressingMode7Bit, "^CH01", 0x00,
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/linux/arch/mips/include/asm/mach-loongson2ef/cs5536/ |
H A D | cs5536_pci.h | 33 #define PCI_BUS_CS5536 0 49 #define CS5536_VENDOR_ID 0x1022 52 #define CS5536_ISA_DEVICE_ID 0x2090 53 #define CS5536_IDE_DEVICE_ID 0x209a 54 #define CS5536_ACC_DEVICE_ID 0x2093 55 #define CS5536_OHCI_DEVICE_ID 0x2094 56 #define CS5536_EHCI_DEVICE_ID 0x2095 59 #define CS5536_ISA_CLASS_CODE 0x060100 60 #define CS5536_IDE_CLASS_CODE 0x010180 61 #define CS5536_ACC_CLASS_CODE 0x040100 [all …]
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/linux/Documentation/devicetree/bindings/phy/ |
H A D | intel,combo-phy.yaml | 18 pattern: "combophy(@.*|-([0-9]|[1-9][0-9]+))?$" 97 reg = <0xd0a00000 0x40000>, 98 <0xd0a40000 0x1000>; 100 resets = <&rcu0 0x50 6>, 101 <&rcu0 0x50 17>, 102 <&rcu0 0x50 23>, 103 <&rcu0 0x50 24>; 105 intel,syscfg = <&sysconf 0>; 106 intel,hsio = <&hsiol 0>;
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/linux/include/dt-bindings/clock/ |
H A D | dra7.h | 8 #define DRA7_CLKCTRL_OFFSET 0x20 12 #define DRA7_MPU_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 15 #define DRA7_DSP1_MMU0_DSP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 18 #define DRA7_IPU1_MMU_IPU1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 21 #define DRA7_IPU_CLKCTRL_OFFSET 0x50 23 #define DRA7_IPU_MCASP1_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x50) 24 #define DRA7_IPU_TIMER5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x58) 25 #define DRA7_IPU_TIMER6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x60) 26 #define DRA7_IPU_TIMER7_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x68) 27 #define DRA7_IPU_TIMER8_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x70) [all …]
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/linux/drivers/char/agp/ |
H A D | intel-agp.h | 9 #define INTEL_APSIZE 0xb4 10 #define INTEL_ATTBASE 0xb8 11 #define INTEL_AGPCTRL 0xb0 12 #define INTEL_NBXCFG 0x50 13 #define INTEL_ERRSTS 0x91 16 #define I830_GMCH_CTRL 0x52 17 #define I830_GMCH_ENABLED 0x4 18 #define I830_GMCH_MEM_MASK 0x1 19 #define I830_GMCH_MEM_64M 0x1 20 #define I830_GMCH_MEM_128M 0 [all …]
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/linux/arch/m68k/atari/ |
H A D | debug.c | 37 while (!(st_mfp.trn_stat & 0x80)) /* wait for tx buf empty */ in ata_mfp_out() 56 } while (!(atari_scc.cha_b_ctrl & 0x04)); /* wait for tx buf empty */ in ata_scc_out() 97 return 0; in ata_par_out() 103 sound_ym.wd_data = tmp & ~0x20; /* set strobe L */ in ata_par_out() 105 sound_ym.wd_data = tmp | 0x20; /* set strobe H */ in ata_par_out() 120 printer_present = 0; in atari_par_console_write() 125 printer_present = 0; in atari_par_console_write() 131 #if 0 134 while (!(st_mfp.rcv_stat & 0x80)) /* wait for rx buf filled */ 143 } while (!(atari_scc.cha_b_ctrl & 0x01)); /* wait for rx buf filled */ [all …]
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/linux/kernel/bpf/preload/iterators/ |
H A D | iterators.lskel-big-endian.h | 27 int fd = skel_link_create(prog_fd, 0, BPF_TRACE_ITER); in iterators_bpf__dump_bpf_map__attach() 29 if (fd > 0) in iterators_bpf__dump_bpf_map__attach() 38 int fd = skel_link_create(prog_fd, 0, BPF_TRACE_ITER); in iterators_bpf__dump_bpf_prog__attach() 40 if (fd > 0) in iterators_bpf__dump_bpf_prog__attach() 48 int ret = 0; in iterators_bpf__attach() 50 ret = ret < 0 ? ret : iterators_bpf__dump_bpf_map__attach(skel); in iterators_bpf__attach() 51 ret = ret < 0 ? ret : iterators_bpf__dump_bpf_prog__attach(skel); in iterators_bpf__attach() 52 return ret < 0 ? ret : 0; in iterators_bpf__attach() 96 \0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\ in iterators_bpf__load() 97 \0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\ in iterators_bpf__load() [all …]
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/linux/drivers/misc/cardreader/ |
H A D | rtl8411.c | 23 return val & 0x0F; in rtl8411_get_ic_version() 28 u8 val = 0; in rtl8411b_is_qfn48() 32 if (val & 0x2) in rtl8411b_is_qfn48() 35 return 0; in rtl8411b_is_qfn48() 41 u32 reg1 = 0; in rtl8411_fetch_vendor_settings() 42 u8 reg3 = 0; in rtl8411_fetch_vendor_settings() 45 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg1); in rtl8411_fetch_vendor_settings() 53 pcr->card_drive_sel &= 0x3F; in rtl8411_fetch_vendor_settings() 57 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG3, reg3); in rtl8411_fetch_vendor_settings() 64 u32 reg = 0; in rtl8411b_fetch_vendor_settings() [all …]
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/linux/arch/sparc/include/uapi/asm/ |
H A D | ptrace.h | 16 #define PT_REGS_MAGIC 0x57ac6c00 142 #define UREG_G0 0 169 #define TRACEREG_SZ 0xa0 170 #define STACKFRAME_SZ 0xc0 172 #define TRACEREG32_SZ 0x50 173 #define STACKFRAME32_SZ 0x60 185 #define TRACEREG_SZ 0x50 186 #define STACKFRAME_SZ 0x60 193 #define PT_V9_G0 0x00 194 #define PT_V9_G1 0x08 [all …]
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/linux/Documentation/misc-devices/ |
H A D | max6875.rst | 51 Valid addresses for the MAX6875 are 0x50 and 0x52. 53 Valid addresses for the MAX6874 are 0x50, 0x52, 0x54 and 0x56. 61 $ echo max6875 0x50 > /sys/bus/i2c/devices/i2c-0/new_device 63 The MAX6874/MAX6875 ignores address bit 0, so this driver attaches to multiple 64 addresses. For example, for address 0x50, it also reserves 0x51. 75 The configuration registers are at addresses 0x00 - 0x45. 84 To write a 1 to register 0x45:: 86 i2c_smbus_write_byte_data(fd, 0x45, 1); 88 To read register 0x45:: 90 value = i2c_smbus_read_byte_data(fd, 0x45); [all …]
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/linux/drivers/gpu/drm/xe/abi/ |
H A D | guc_errors_abi.h | 10 XE_GUC_RESPONSE_STATUS_SUCCESS = 0x0, 11 XE_GUC_RESPONSE_ERROR_PROTOCOL = 0x04, 12 XE_GUC_RESPONSE_INVALID_STATE = 0x0A, 13 XE_GUC_RESPONSE_UNSUPPORTED_VERSION = 0x0B, 14 XE_GUC_RESPONSE_INVALID_VFID = 0x0C, 15 XE_GUC_RESPONSE_UNPROVISIONED_VF = 0x0D, 16 XE_GUC_RESPONSE_INVALID_EVENT = 0x0E, 17 XE_GUC_RESPONSE_NOT_SUPPORTED = 0x20, 18 XE_GUC_RESPONSE_UNKNOWN_ACTION = 0x30, 19 XE_GUC_RESPONSE_ACTION_ABORTED = 0x31, [all …]
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/linux/arch/mips/boot/dts/pic32/ |
H A D | pic32mzda.dtsi | 34 #size-cells = <0>; 36 cpu@0 { 44 interrupts = <0 IRQ_TYPE_EDGE_RISING>; 49 #clock-cells = <0>; 57 #clock-cells = <0>; 65 reg = <0x1f801200 0x200>; 74 reg = <0x1f810000 0x1000>; 82 reg = <0x1f801400 0x400>; 89 reg = <0x1f860000 0x100>; 96 microchip,gpio-bank = <0>; [all …]
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/linux/fs/nls/ |
H A D | nls_ascii.c | 17 /* 0x00*/ 18 0x0000, 0x0001, 0x0002, 0x0003, 19 0x0004, 0x0005, 0x0006, 0x0007, 20 0x0008, 0x0009, 0x000a, 0x000b, 21 0x000c, 0x000d, 0x000e, 0x000f, 22 /* 0x10*/ 23 0x0010, 0x0011, 0x0012, 0x0013, 24 0x0014, 0x0015, 0x0016, 0x0017, 25 0x0018, 0x0019, 0x001a, 0x001b, 26 0x001c, 0x001d, 0x001e, 0x001f, [all …]
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/linux/arch/arm/boot/dts/aspeed/ |
H A D | aspeed-bmc-ibm-bonnell.dts | 29 reg = <0x80000000 0x40000000>; 39 reg = <0xb3d00000 0x100000>; 44 reg = <0xb3e00000 0x200000>; /* 16 * (4 * 0x8000) */ 45 record-size = <0x8000>; 46 console-size = <0x8000>; 47 ftrace-size = <0x8000>; 48 pmsg-size = <0x8000>; 55 reg = <0xb4000000 0x04000000>; /* 64M */ 62 reg = <0xbf000000 0x01000000>; /* 16M */ 70 gpios = <&gpio0 ASPEED_GPIO(G, 0) GPIO_ACTIVE_LOW>; [all …]
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