| /linux/arch/s390/boot/ |
| H A D | ipl_data.c | 15 psw_t32 ipl_psw; /* 0x0000 */
16 struct ccw0 ccwpgm[2]; /* 0x0008 */
17 u8 fill[56]; /* 0x0018 */
18 struct ccw0 ccwpgmcc[20]; /* 0x0050 */
19 u8 pad_0xf0[0x0140-0x00f0]; /* 0x00f0 */
20 psw_t svc_old_psw; /* 0x0140 */
21 u8 pad_0x150[0x01a0-0x0150]; /* 0x0150 */
22 psw_t restart_psw; /* 0x01a0 */
23 psw_t external_new_psw; /* 0x01b0 */
24 psw_t svc_new_psw; /* 0x01c0 */
[all …]
|
| /linux/drivers/media/dvb-frontends/ |
| H A D | mb86a20s.c | 18 MB86A20S_13SEG = 0,
25 0xb0, 0xc0, 0xd0, 0xe0,
26 0xf0, 0x00, 0x10, 0x20,
59 { 0x70, 0x0f },
60 { 0x70, 0xff },
61 { 0x08, 0x01 },
62 { 0x50, 0xd1 }, { 0x51, 0x20 },
66 { 0x50, 0xd1 }, { 0x51, 0x22 },
67 { 0x39, 0x01 },
68 { 0x71, 0x00 },
[all …]
|
| /linux/Documentation/ABI/testing/ |
| H A D | debugfs-iio-backend | 13 Reading address 0x50
14 echo 0x50 > direct_reg_access
17 Writing address 0x50
18 echo 0x50 0x3 > direct_reg_access
19 //readback address 0x50
|
| /linux/drivers/gpu/drm/panel/ |
| H A D | panel-novatek-nt36672a.c | 89 for (i = 0; i < num; i++) { in nt36672a_send_cmds()
92 err = mipi_dsi_dcs_write(pinfo->link, cmd->data[0], cmd->data + 1, 1); in nt36672a_send_cmds()
94 if (err < 0) in nt36672a_send_cmds()
98 return 0; in nt36672a_send_cmds()
104 int ret = 0; in nt36672a_panel_power_off()
124 if (ret < 0) in nt36672a_panel_unprepare()
128 if (ret < 0) in nt36672a_panel_unprepare()
135 if (ret < 0) in nt36672a_panel_unprepare()
138 /* 0x3C = 60ms delay */ in nt36672a_panel_unprepare()
142 if (ret < 0) in nt36672a_panel_unprepare()
[all …]
|
| /linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
| H A D | dp.h | 12 #define DPCD_RC00_DPCD_REV 0x00000
13 #define DPCD_RC01_MAX_LINK_RATE 0x00001
14 #define DPCD_RC02 0x00002
15 #define DPCD_RC02_ENHANCED_FRAME_CAP 0x80
16 #define DPCD_RC02_TPS3_SUPPORTED 0x40
17 #define DPCD_RC02_MAX_LANE_COUNT 0x1f
18 #define DPCD_RC03 0x00003
19 #define DPCD_RC03_TPS4_SUPPORTED 0x80
20 #define DPCD_RC03_MAX_DOWNSPREAD 0x01
21 #define DPCD_RC0E 0x0000e
[all …]
|
| /linux/drivers/media/tuners/ |
| H A D | fc2580_priv.h | 23 {0x00, 0x00},
24 {0x12, 0x86},
25 {0x14, 0x5c},
26 {0x16, 0x3c},
27 {0x1f, 0xd2},
28 {0x09, 0xd7},
29 {0x0b, 0xd5},
30 {0x0c, 0x32},
31 {0x0e, 0x43},
32 {0x21, 0x0a},
[all …]
|
| /linux/Documentation/firmware-guide/acpi/ |
| H A D | i2c-muxes.rst | 13 | SMB1 |-->| MUX0 |--CH00--> i2c client A (0x50)
14 | | | 0x70 |--CH01--> i2c client B (0x50)
26 I2cSerialBus (0x70, ControllerInitiated, I2C_SPEED,
27 AddressingMode7Bit, "\\_SB.SMB1", 0x00,
33 Name (_ADR, 0)
39 I2cSerialBus (0x50, ControllerInitiated, I2C_SPEED,
40 AddressingMode7Bit, "\\_SB.SMB1.CH00", 0x00,
54 I2cSerialBus (0x50, ControllerInitiated, I2C_SPEED,
55 AddressingMode7Bit, "\\_SB.SMB1.CH01", 0x00,
|
| /linux/drivers/pinctrl/mediatek/ |
| H A D | pinctrl-mt8135.c | 17 #define DRV_BASE1 0x500
18 #define DRV_BASE2 0x510
19 #define PUPD_BASE1 0x400
20 #define PUPD_BASE2 0x450
21 #define R0_BASE1 0x4d0
22 #define R1_BASE1 0x200
23 #define R1_BASE2 0x250
49 MTK_DRV_GRP(2, 16, 0, 2, 2),
53 MTK_DRV_GRP(2, 8, 0, 1, 2),
55 MTK_DRV_GRP(4, 32, 0, 2, 4)
[all …]
|
| H A D | pinctrl-mt8173.c | 18 #define DRV_BASE 0xb00
21 MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 2, 1, 0), /* KROW0 */
22 MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 6, 5, 4), /* KROW1 */
23 MTK_PIN_PUPD_SPEC_SR(121, 0xe00, 10, 9, 8), /* KROW2 */
24 MTK_PIN_PUPD_SPEC_SR(122, 0xe10, 2, 1, 0), /* KCOL0 */
25 MTK_PIN_PUPD_SPEC_SR(123, 0xe10, 6, 5, 4), /* KCOL1 */
26 MTK_PIN_PUPD_SPEC_SR(124, 0xe10, 10, 9, 8), /* KCOL2 */
28 MTK_PIN_PUPD_SPEC_SR(67, 0xd10, 2, 1, 0), /* ms0 DS */
29 MTK_PIN_PUPD_SPEC_SR(68, 0xd00, 2, 1, 0), /* ms0 RST */
30 MTK_PIN_PUPD_SPEC_SR(66, 0xc10, 2, 1, 0), /* ms0 cmd */
[all …]
|
| /linux/crypto/ |
| H A D | testmgr.h | 34 * @ksize: Length of @key in bytes (0 if no key)
101 * @crypt_error: When @novrfy=0, the expected error from encrypt(). When
231 "\x5e\x32\x39\x6d\xc1\x1d\x7d\x50\x3b\x9f\x7a\xad\xf0\x2e\x25\x53"
256 "\xC9\x7F\xF3\xAD\x59\x50\xAC\xCF\xBC\x11\x1C\x76\xF1\xA9\x52\x94"
285 "\xB3\x80\xF2\x71\xF7\x34\x53\x88\x50\x93\x07\x7F\xCD\x39\xE2\x11"
296 "\x59\x89\xaf\xf0\xba\x44\xd7\xf1\x1a\x50\x72\xef\x5e\x4a\xb6\xb7"
370 "\xC2\x18\xB1\x58\xB1\x50\x91\xB8\x61\x41\xB6\xA9\xCE\xD4\x7C\xBB"
388 "\x51\x2A\x5D\x14\x2F\x41\x25\x00\xDD\xF8\xF3\x95\xFE\x31\x25\x50"
461 "\xA0\x86\xED\xF2\xB9\x50\x5C\x54\x5C\xBA\xE4\xA1\xB2\xA7\xAE\x2F"
499 "\x24\x3A\xC9\xCF\x6D\x8D\x17\x50\x94\x52\xD3\xE7\x0F\x2F\x7E\x94"
[all …]
|
| /linux/arch/mips/include/asm/mach-loongson2ef/cs5536/ |
| H A D | cs5536_pci.h | 53 #define PCI_BUS_CS5536 0
69 #define CS5536_VENDOR_ID 0x1022
72 #define CS5536_ISA_DEVICE_ID 0x2090
73 #define CS5536_IDE_DEVICE_ID 0x209a
74 #define CS5536_ACC_DEVICE_ID 0x2093
75 #define CS5536_OHCI_DEVICE_ID 0x2094
76 #define CS5536_EHCI_DEVICE_ID 0x2095
79 #define CS5536_ISA_CLASS_CODE 0x060100
80 #define CS5536_IDE_CLASS_CODE 0x010180
81 #define CS5536_ACC_CLASS_CODE 0x040100
[all …]
|
| /linux/Documentation/devicetree/bindings/phy/ |
| H A D | intel,combo-phy.yaml | 18 pattern: "combophy(@.*|-([0-9]|[1-9][0-9]+))?$"
97 reg = <0xd0a00000 0x40000>,
98 <0xd0a40000 0x1000>;
100 resets = <&rcu0 0x50 6>,
101 <&rcu0 0x50 17>,
102 <&rcu0 0x50 23>,
103 <&rcu0 0x50 24>;
105 intel,syscfg = <&sysconf 0>;
106 intel,hsio = <&hsiol 0>;
|
| /linux/include/dt-bindings/clock/ |
| H A D | dra7.h | 8 #define DRA7_CLKCTRL_OFFSET 0x20
12 #define DRA7_MPU_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
15 #define DRA7_DSP1_MMU0_DSP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
18 #define DRA7_IPU1_MMU_IPU1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
21 #define DRA7_IPU_CLKCTRL_OFFSET 0x50
23 #define DRA7_IPU_MCASP1_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x50)
24 #define DRA7_IPU_TIMER5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x58)
25 #define DRA7_IPU_TIMER6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x60)
26 #define DRA7_IPU_TIMER7_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x68)
27 #define DRA7_IPU_TIMER8_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x70)
[all …]
|
| /linux/drivers/char/agp/ |
| H A D | intel-agp.h | 9 #define INTEL_APSIZE 0xb4
10 #define INTEL_ATTBASE 0xb8
11 #define INTEL_AGPCTRL 0xb0
12 #define INTEL_NBXCFG 0x50
13 #define INTEL_ERRSTS 0x91
16 #define I830_GMCH_CTRL 0x52
17 #define I830_GMCH_ENABLED 0x4
18 #define I830_GMCH_MEM_MASK 0x1
19 #define I830_GMCH_MEM_64M 0x1
20 #define I830_GMCH_MEM_128M 0
[all …]
|
| /linux/arch/m68k/atari/ |
| H A D | debug.c | 37 while (!(st_mfp.trn_stat & 0x80)) /* wait for tx buf empty */ in ata_mfp_out()
56 } while (!(atari_scc.cha_b_ctrl & 0x04)); /* wait for tx buf empty */ in ata_scc_out()
97 return 0; in ata_par_out()
103 sound_ym.wd_data = tmp & ~0x20; /* set strobe L */ in ata_par_out()
105 sound_ym.wd_data = tmp | 0x20; /* set strobe H */ in ata_par_out()
120 printer_present = 0; in atari_par_console_write()
125 printer_present = 0; in atari_par_console_write()
131 #if 0
134 while (!(st_mfp.rcv_stat & 0x80)) /* wait for rx buf filled */
143 } while (!(atari_scc.cha_b_ctrl & 0x01)); /* wait for rx buf filled */
[all …]
|
| /linux/drivers/clk/ |
| H A D | clk-loongson2.c | 142 CLK_PLL(LS2K0300_NODE_PLL, "pll_node", 0x00, 15, 9, 8, 7),
143 CLK_PLL(LS2K0300_DDR_PLL, "pll_ddr", 0x08, 15, 9, 8, 7),
144 CLK_PLL(LS2K0300_PIX_PLL, "pll_pix", 0x10, 15, 9, 8, 7),
148 CLK_DIV(LS2K0300_CLK_NODE_DIV, "clk_node_div", "pll_node", 0x00, 24, 7),
149 CLK_DIV(LS2K0300_CLK_GMAC_DIV, "clk_gmac_div", "pll_node", 0x04, 0, 7),
150 CLK_DIV(LS2K0300_CLK_I2S_DIV, "clk_i2s_div", "pll_node", 0x04, 8, 7),
151 CLK_GATE(LS2K0300_CLK_NODE_PLL_GATE, "clk_node_pll_gate", "clk_node_div", 0x00, 0),
152 CLK_GATE(LS2K0300_CLK_GMAC_GATE, "clk_gmac_gate", "clk_gmac_div", 0x00, 1),
153 CLK_GATE(LS2K0300_CLK_I2S_GATE, "clk_i2s_gate", "clk_i2s_div", 0x00, 2),
154 CLK_GATE_FLAGS(LS2K0300_CLK_NODE_GATE, "clk_node_gate", "clk_node_scale", 0x24, 0,
[all …]
|
| /linux/drivers/misc/cardreader/ |
| H A D | rtl8411.c | 23 return val & 0x0F; in rtl8411_get_ic_version()
28 u8 val = 0; in rtl8411b_is_qfn48()
32 if (val & 0x2) in rtl8411b_is_qfn48()
35 return 0; in rtl8411b_is_qfn48()
41 u32 reg1 = 0; in rtl8411_fetch_vendor_settings()
42 u8 reg3 = 0; in rtl8411_fetch_vendor_settings()
45 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg1); in rtl8411_fetch_vendor_settings()
53 pcr->card_drive_sel &= 0x3F; in rtl8411_fetch_vendor_settings()
57 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG3, reg3); in rtl8411_fetch_vendor_settings()
64 u32 reg = 0; in rtl8411b_fetch_vendor_settings()
[all …]
|
| /linux/Documentation/misc-devices/ |
| H A D | max6875.rst | 51 Valid addresses for the MAX6875 are 0x50 and 0x52.
53 Valid addresses for the MAX6874 are 0x50, 0x52, 0x54 and 0x56.
61 $ echo max6875 0x50 > /sys/bus/i2c/devices/i2c-0/new_device
63 The MAX6874/MAX6875 ignores address bit 0, so this driver attaches to multiple
64 addresses. For example, for address 0x50, it also reserves 0x51.
75 The configuration registers are at addresses 0x00 - 0x45.
84 To write a 1 to register 0x45::
86 i2c_smbus_write_byte_data(fd, 0x45, 1);
88 To read register 0x45::
90 value = i2c_smbus_read_byte_data(fd, 0x45);
[all …]
|
| /linux/arch/mips/boot/dts/pic32/ |
| H A D | pic32mzda.dtsi | 34 #size-cells = <0>;
36 cpu@0 {
44 interrupts = <0 IRQ_TYPE_EDGE_RISING>;
49 #clock-cells = <0>;
57 #clock-cells = <0>;
65 reg = <0x1f801200 0x200>;
74 reg = <0x1f810000 0x1000>;
82 reg = <0x1f801400 0x400>;
89 reg = <0x1f860000 0x100>;
96 microchip,gpio-bank = <0>;
[all …]
|
| /linux/fs/nls/ |
| H A D | nls_ascii.c | 17 /* 0x00*/
18 0x0000, 0x0001, 0x0002, 0x0003,
19 0x0004, 0x0005, 0x0006, 0x0007,
20 0x0008, 0x0009, 0x000a, 0x000b,
21 0x000c, 0x000d, 0x000e, 0x000f,
22 /* 0x10*/
23 0x0010, 0x0011, 0x0012, 0x0013,
24 0x0014, 0x0015, 0x0016, 0x0017,
25 0x0018, 0x0019, 0x001a, 0x001b,
26 0x001c, 0x001d, 0x001e, 0x001f,
[all …]
|
| /linux/arch/arm/boot/dts/aspeed/ |
| H A D | aspeed-bmc-ibm-bonnell.dts | 29 reg = <0x80000000 0x40000000>;
39 reg = <0xb3d00000 0x100000>;
44 reg = <0xb3e00000 0x200000>; /* 16 * (4 * 0x8000) */
45 record-size = <0x8000>;
46 console-size = <0x8000>;
47 ftrace-size = <0x8000>;
48 pmsg-size = <0x8000>;
55 reg = <0xb4000000 0x04000000>; /* 64M */
62 reg = <0xbf000000 0x01000000>; /* 16M */
70 gpios = <&gpio0 ASPEED_GPIO(G, 0) GPIO_ACTIVE_LOW>;
[all …]
|
| /linux/drivers/mtd/nand/raw/ |
| H A D | denali.h | 17 #define DEVICE_RESET 0x0
20 #define TRANSFER_SPARE_REG 0x10
21 #define TRANSFER_SPARE_REG__FLAG BIT(0)
23 #define LOAD_WAIT_CNT 0x20
24 #define LOAD_WAIT_CNT__VALUE GENMASK(15, 0)
26 #define PROGRAM_WAIT_CNT 0x30
27 #define PROGRAM_WAIT_CNT__VALUE GENMASK(15, 0)
29 #define ERASE_WAIT_CNT 0x40
30 #define ERASE_WAIT_CNT__VALUE GENMASK(15, 0)
32 #define INT_MON_CYCCNT 0x50
[all …]
|
| /linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
| H A D | ctxnv50.c | 23 #define CP_FLAG_CLEAR 0
25 #define CP_FLAG_SWAP_DIRECTION ((0 * 32) + 0)
26 #define CP_FLAG_SWAP_DIRECTION_LOAD 0
28 #define CP_FLAG_UNK01 ((0 * 32) + 1)
29 #define CP_FLAG_UNK01_CLEAR 0
31 #define CP_FLAG_UNK03 ((0 * 32) + 3)
32 #define CP_FLAG_UNK03_CLEAR 0
34 #define CP_FLAG_USER_SAVE ((0 * 32) + 5)
35 #define CP_FLAG_USER_SAVE_NOT_PENDING 0
37 #define CP_FLAG_USER_LOAD ((0 * 32) + 6)
[all …]
|
| /linux/drivers/staging/rtl8723bs/core/ |
| H A D | rtw_ieee80211.c | 12 u8 RTW_WPA_OUI_TYPE[] = { 0x00, 0x50, 0xf2, 1 };
14 u8 WPA_AUTH_KEY_MGMT_NONE[] = { 0x00, 0x50, 0xf2, 0 };
15 u8 WPA_AUTH_KEY_MGMT_UNSPEC_802_1X[] = { 0x00, 0x50, 0xf2, 1 };
16 u8 WPA_AUTH_KEY_MGMT_PSK_OVER_802_1X[] = { 0x00, 0x50, 0xf2, 2 };
17 u8 WPA_CIPHER_SUITE_NONE[] = { 0x00, 0x50, 0xf2, 0 };
18 u8 WPA_CIPHER_SUITE_WEP40[] = { 0x00, 0x50, 0xf2, 1 };
19 u8 WPA_CIPHER_SUITE_TKIP[] = { 0x00, 0x50, 0xf2, 2 };
20 u8 WPA_CIPHER_SUITE_WRAP[] = { 0x00, 0x50, 0xf2, 3 };
21 u8 WPA_CIPHER_SUITE_CCMP[] = { 0x00, 0x50, 0xf2, 4 };
22 u8 WPA_CIPHER_SUITE_WEP104[] = { 0x00, 0x50, 0xf2, 5 };
[all …]
|
| /linux/drivers/net/wireless/intersil/p54/ |
| H A D | p54spi_eeprom.h | 19 0x47, 0x4d, 0x55, 0xaa, /* magic */
20 0x00, 0x00, /* pad */
21 0x00, 0x00, /* eeprom_pda_data_wrap length */
22 0x00, 0x00, 0x00, 0x00, /* arm opcode */
25 0x04, 0x00, 0x01, 0x01, /* PDR_MAC_ADDRESS */
26 0x00, 0x02, 0xee, 0xc0, 0xff, 0xee,
29 0x06, 0x00, 0x01, 0x10, /* PDR_INTERFACE_LIST */
30 0x00, 0x00, /* role */
31 0x0f, 0x00, /* if_id */
32 0x85, 0x00, /* variant = Longbow RF, 2GHz */
[all …]
|