/titanic_50/usr/src/lib/libkmf/libkmf/common/ |
H A D | kmfoids.c | 13 OID_ObjectClass[] = { OID_ATTR_TYPE, 0 }, 411 #define RSADSI 0x2a, 0x86, 0x48, 0x86, 0xf7, 0x0d 412 #define OID_id_md5 RSADSI, 0x02, 0x05 430 #define CERTICOM_OID 0x2b, 0x81, 0x04 431 #define SECG_OID CERTICOM_OID, 0x00 433 #define ANSI_X962_OID 0x2a, 0x86, 0x48, 0xce, 0x3d 434 #define ANSI_X962_CURVE_OID ANSI_X962_OID, 0x03 435 #define ANSI_X962_GF2m_OID ANSI_X962_CURVE_OID, 0x00 436 #define ANSI_X962_GFp_OID ANSI_X962_CURVE_OID, 0x01 438 #define ANSI_X962_SIG_OID ANSI_X962_OID, 0x04 [all …]
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/titanic_50/usr/src/uts/common/io/chxge/com/ |
H A D | vsc7326_reg.h | 39 #define CRA(blk,sub,adr) ((((blk) & 0x7) << 13) | (((sub) & 0xf) << 9) | (((adr) & 0xff) << 1)) 42 #define REG_CHIP_ID CRA(0x7,0xf,0x00) /* Chip ID */ 43 #define REG_BLADE_ID CRA(0x7,0xf,0x01) /* Blade ID */ 44 #define REG_SW_RESET CRA(0x7,0xf,0x02) /* Global Soft Reset */ 45 #define REG_MEM_BIST CRA(0x7,0xf,0x04) /* mem */ 46 #define REG_IFACE_MODE CRA(0x7,0xf,0x07) /* Interface mode */ 47 #define REG_MSCH CRA(0x7,0x2,0x06) /* CRC error count */ 48 #define REG_CRC_CNT CRA(0x7,0x2,0x0a) /* CRC error count */ 49 #define REG_CRC_CFG CRA(0x7,0x2,0x0b) /* CRC config */ 50 #define REG_SI_TRANSFER_SEL CRA(0x7,0xf,0x18) /* SI Transfer Select */ [all …]
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H A D | vsc7321_reg.h | 39 #define CRA(blk,sub,adr) ((((blk) & 0x7) << 13) | (((sub) & 0xf) << 9) | (((adr) & 0xff) << 1)) 42 #define REG_CHIP_ID CRA(0x7,0xf,0x00) /* Chip ID */ 43 #define REG_BLADE_ID CRA(0x7,0xf,0x01) /* Blade ID */ 44 #define REG_SW_RESET CRA(0x7,0xf,0x02) /* Global Soft Reset */ 45 #define REG_IFACE_MODE CRA(0x7,0xf,0x07) /* Interface mode */ 46 #define REG_CRC_CNT CRA(0x7,0xf,0x0a) /* CRC error count */ 47 #define REG_CRC_CFG CRA(0x7,0xf,0x0b) /* CRC config */ 48 #define REG_SI_TRANSFER_SEL CRA(0x7,0xf,0x18) /* SI Transfer Select */ 49 #define REG_PLL_CLK_SPEED CRA(0x7,0xf,0x19) /* Clock Speed Selection */ 50 #define REG_SYS_CLK_SELECT CRA(0x7,0xf,0x1c) /* System Clock Select */ [all …]
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/titanic_50/usr/src/uts/sun4v/io/px/ |
H A D | px_err.h | 36 #define BLOCK_RSVD 0x0 37 #define BLOCK_HOSTBUS 0x1 38 #define BLOCK_MMU 0x2 39 #define BLOCK_INTR 0x3 40 #define BLOCK_PCIE 0x4 41 #define BLOCK_PORT 0x5 42 #define BLOCK_UNKNOWN 0xe 45 #define OP_RESERVED 0x0 46 #define OP_PIO 0x1 47 #define OP_DMA 0x2 [all …]
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/titanic_50/usr/src/common/crypto/chacha/ |
H A D | chacha.c | 19 #define U8V(v) ((u8)(v) & U8C(0xFF)) 20 #define U32V(v) ((u32)(v) & U32C(0xFFFFFFFF)) 26 (((u32)((p)[0]) ) | \ 33 (p)[0] = U8V((v) ); \ 37 } while (0) 58 x->chacha_input[4] = U8TO32_LITTLE(k + 0); in chacha_keysetup() 68 x->chacha_input[8] = U8TO32_LITTLE(k + 0); in chacha_keysetup() 72 x->chacha_input[0] = U8TO32_LITTLE(constants + 0); in chacha_keysetup() 81 x->chacha_input[12] = 0; in chacha_ivsetup() 82 x->chacha_input[13] = 0; in chacha_ivsetup() [all …]
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/titanic_50/usr/src/uts/common/sys/dcam/ |
H A D | dcam1394_io.h | 41 #define PARAM_LIST_REMOVE(list, param, subparam) list[param][subparam].flag = 0 50 #define DCAM1394_PARAM_CAP_POWER_CTRL 0x0 51 #define DCAM1394_PARAM_CAP_VID_MODE 0x1 52 #define DCAM1394_PARAM_CAP_FRAME_RATE_VID_MODE_0 0x2 53 #define DCAM1394_PARAM_CAP_FRAME_RATE_VID_MODE_1 0x3 54 #define DCAM1394_PARAM_CAP_FRAME_RATE_VID_MODE_2 0x4 55 #define DCAM1394_PARAM_CAP_FRAME_RATE_VID_MODE_3 0x5 56 #define DCAM1394_PARAM_CAP_FRAME_RATE_VID_MODE_4 0x6 57 #define DCAM1394_PARAM_CAP_FRAME_RATE_VID_MODE_5 0x7 58 #define DCAM1394_PARAM_POWER 0x8 [all …]
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/titanic_50/usr/src/cmd/dtrace/test/tst/common/print/ |
H A D | tst.array.d.out | 1 int [3] [ 0x1, 0x2, 0x3 ] 5 int alpha = 0x5 8 int alpha = 0x6 12 int [3] a = [ 0x1, 0x2, 0x3 ] 16 int alpha = 0x5 19 int alpha = 0x6 22 char [3] d = [ '\004', '\0', '\0' ]
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/titanic_50/usr/src/uts/sun4u/io/ |
H A D | panther_asm.s | 137 {return 0;} 163 btst 0x7, %o3 186 and %o3, 0x7, %o3 187 cmp %o3, 0x5 191 cmp %o5, 0 210 {return 0;} 235 and %o3, 0x7, %o3 236 cmp %o3, 0x5 267 {return 0;} 293 btst 0x7, %o3 [all …]
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/titanic_50/usr/src/uts/sun4/io/fpc/ |
H A D | fpc.h | 36 #define SUCCESS 0 53 jbc = 0, 79 #define PIC0_EVT_SEL_SHIFT 0 85 #define JBC01_EVT_MASK 0xFF 86 #define IMU01_EVT_MASK 0xFF 87 #define MMU01_EVT_MASK 0xFF 88 #define TLU01_EVT_MASK 0xFF 89 #define TLU2_EVT_MASK 0x3 90 #define LPU12_EVT_MASK 0xFFFF 116 #define JBUS_REGS_AVAIL 0x1 /* JBUS regs avail */ [all …]
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/titanic_50/usr/src/uts/common/io/usb/clients/hidparser/ |
H A D | README | 106 hid1: Index = 0 value =0x5 107 hid1: Index = 1 value =0x1 108 hid1: Index = 2 value =0x9 109 hid1: Index = 3 value =0x8 110 hid1: Index = 4 value =0xa1 111 hid1: Index = 5 value =0x1 112 hid1: Index = 6 value =0xa1 113 hid1: Index = 7 value =0x0 114 hid1: Index = 8 value =0x85 115 hid1: Index = 9 value =0x1 [all …]
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/titanic_50/usr/src/uts/common/inet/ |
H A D | wifi_ioctl.h | 41 /* one more for '\0' */ 52 #define WLAN_IOCTL_BASE 0x1000 53 #define WLAN_GET_VERSION (WLAN_IOCTL_BASE + 0x0) 54 #define WLAN_SET_PARAM (WLAN_IOCTL_BASE + 0x2) 55 #define WLAN_GET_PARAM (WLAN_IOCTL_BASE + 0x3) 56 #define WLAN_COMMAND (WLAN_IOCTL_BASE + 0x4) 61 #define WL_PARAMETERS_BASE 0x2000 62 #define WL_BSSID (WL_PARAMETERS_BASE + 0x0) 63 #define WL_ESSID (WL_PARAMETERS_BASE + 0x1) 64 #define WL_NODE_NAME (WL_PARAMETERS_BASE + 0x2) [all …]
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/titanic_50/usr/src/uts/common/sys/sata/ |
H A D | sata_blacklist.h | 37 * The number of the device ports is indicated by GSCR2[3:0]. These port 54 {0x37261095, 0x0, 0x6, 0x5}, /* Silicon Image 3726, 5 ports. */ 55 {0x47261095, 0x0, 0x7, 0x5}, /* Silicon Image 4726, 5 ports. */ 56 {0x47231095, 0x0, 0x4, 0x2}, /* Silicon Image 4723, 2 ports. */
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/titanic_50/usr/src/uts/intel/pcbe/ |
H A D | p4_pcbe.c | 122 #define P4_THIS_USR 0x1 /* HTT: Measure usr events on this logical CPU */ 123 #define P4_THIS_SYS 0x2 /* HTT: Measure os events on this logical CPU */ 124 #define P4_SIBLING_USR 0x4 /* HTT: Measure os events on other logical CPU */ 125 #define P4_SIBLING_SYS 0x8 /* HTT: Measure usr events on other logical CPU */ 126 #define P4_PMI 0x10 /* HTT: Set PMI bit for local logical CPU */ 130 uint8_t p4_picno; /* From 0 to 18 */ 142 uint32_t pe_map; /* bitmap of counters; bit 1 means ctr 0 */ 145 #define MASK40 UINT64_C(0xffffffffff) 164 #define CCCR_ACTV_THR_MASK 0x3 165 #define CCCR_THRESHOLD_MAX 0xF [all …]
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/titanic_50/usr/src/lib/libmvec/common/ |
H A D | __vexp.c | 34 * Write x = (k + j/256)ln2 + r, where k and j are integers, j >= 0, 332 { DBLWORD(0x43380000, 0x00000000) }, 333 { DBLWORD(0x40771547, 0x652b82fe) }, 334 { DBLWORD(0x3f662e42, 0xfee00000) }, 335 { DBLWORD(0x3d6a39ef, 0x35793c76) }, 336 { DBLWORD(0x3ff00000, 0x00000000) }, 337 { DBLWORD(0x3fdfffff, 0xfffffff6) }, 338 { DBLWORD(0x3fc55555, 0x721a1d14) }, 339 { DBLWORD(0x3fa55555, 0x6e0896af) }, 340 { DBLWORD(0x01000000, 0x00000000) }, [all …]
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/titanic_50/usr/src/uts/sun4v/io/iospc/ |
H A D | rfios_tables.h | 90 #define RFIOS_IMU_CTR_EVT_MASK 0xffull 91 #define RFIOS_IMU_CTR_0_EVT_OFF 0 94 #define RFIOS_ATU_CTR_EVT_MASK 0xffull 95 #define RFIOS_ATU_CTR_0_EVT_OFF 0 98 #define RFIOS_NPU_CTR_EVT_MASK 0xffull 99 #define RFIOS_NPU_CTR_0_EVT_OFF 0 102 #define RFIOS_PEX_CTR_EVT_MASK 0xffull 103 #define RFIOS_PEX_CTR_0_EVT_OFF 0 106 #define RFIOS_PEU_CTR_EVT_MASK 0x7full 107 #define RFIOS_PEU_CTR_0_EVT_OFF 0 [all …]
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/titanic_50/usr/src/uts/common/sys/ |
H A D | pci.h | 37 #define PCI_CONF_VENID 0x0 /* vendor id, 2 bytes */ 38 #define PCI_CONF_DEVID 0x2 /* device id, 2 bytes */ 39 #define PCI_CONF_COMM 0x4 /* command register, 2 bytes */ 40 #define PCI_CONF_STAT 0x6 /* status register, 2 bytes */ 41 #define PCI_CONF_REVID 0x8 /* revision id, 1 byte */ 42 #define PCI_CONF_PROGCLASS 0x9 /* programming class code, 1 byte */ 43 #define PCI_CONF_SUBCLASS 0xA /* sub-class code, 1 byte */ 44 #define PCI_CONF_BASCLASS 0xB /* basic class code, 1 byte */ 45 #define PCI_CONF_CACHE_LINESZ 0xC /* cache line size, 1 byte */ 46 #define PCI_CONF_LATENCY_TIMER 0xD /* latency timer, 1 byte */ [all …]
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H A D | swap.h | 122 #define ST_INDEL 0x01 /* Deletion of file is in progress. */ 125 #define ST_DOINGDEL 0x02 /* Set during deletion of file */ 189 * 63 15 14 4 3 0 206 #define SA_NOT 0x01 /* Must have slot from swap dev other than input one */ 227 #define SW_RENAME 0x01 228 #define SW_RESV 0x02 229 #define SW_ALLOC 0x04 230 #define SW_CTL 0x08 231 #define SWAP_PRINT(f, s, x1, x2, x3, x4, x5) \ argument 233 printf(s, x1, x2, x3, x4, x5); [all …]
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/titanic_50/usr/src/uts/common/io/nvme/ |
H A D | nvme_reg.h | 41 #define NVME_REG_CAP 0x0 /* Controller Capabilities */ 42 #define NVME_REG_VS 0x8 /* Version */ 43 #define NVME_REG_INTMS 0xc /* Interrupt Mask Set */ 44 #define NVME_REG_INTMC 0x10 /* Interrupt Mask Clear */ 45 #define NVME_REG_CC 0x14 /* Controller Configuration */ 46 #define NVME_REG_CSTS 0x1c /* Controller Status */ 47 #define NVME_REG_NSSR 0x20 /* NVM Subsystem Reset */ 48 #define NVME_REG_AQA 0x24 /* Admin Queue Attributes */ 49 #define NVME_REG_ASQ 0x28 /* Admin Submission Queue */ 50 #define NVME_REG_ACQ 0x30 /* Admin Completion Qeueu */ [all …]
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/titanic_50/usr/src/uts/sun4v/sys/ |
H A D | niagara2regs.h | 39 #define NIAGARA2_HSVC_MINOR 0 42 #define VFALLS_HSVC_MINOR 0 45 #define KT_HSVC_MINOR 0 50 #define SAMPLE_PIC_IN_OV_RANGE(x) (((uint32_t)x >= 0xfffffffe) ? 1 : 0) 55 #define PIC_IN_OV_RANGE(x) (((uint32_t)x >= 0xfffffff0) ? 1 : 0) 60 #define PIC0_MASK (((uint64_t)1 << 32) - 1) /* pic0 in bits 31:0 */ 66 #define CPC_PCR_PRIV_SHIFT 0 80 #define CPC_PCR_PIC0_MASK UINT64_C(0xfff) 81 #define CPC_PCR_PIC1_MASK UINT64_C(0xfff) 85 #define CPC_PCR_OV0_MASK UINT64_C(0x40000) [all …]
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/titanic_50/usr/src/uts/sun4u/starcat/sys/ |
H A D | dr_mbx.h | 42 #define DRMBX_VERSION 0x0016 55 #define DRMSG_BOARDEVENT 0x1 /* must be 0x1 in every vesion */ 56 #define DRMSG_MBOX_INIT 0x2 /* must be 0x2 in every version */ 57 #define DRMSG_ASSIGN 0x3 58 #define DRMSG_UNASSIGN 0x4 59 #define DRMSG_CLAIM 0x5 60 #define DRMSG_UNCLAIM 0x6 61 #define DRMSG_POWERON 0x7 62 #define DRMSG_POWEROFF 0x8 63 #define DRMSG_TESTBOARD 0x9 [all …]
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/titanic_50/usr/src/uts/common/sys/nxge/ |
H A D | nxge_phy_hw.h | 35 * Clause 45 and Clause 22 port/phy addresses 0 through 5 are reserved 48 #define BCM8704_CHIP_ID 0x8704 49 #define BCM8706_CHIP_ID 0x8706 50 #define MRVL88X201X_CHIP_ID 0x5043 51 #define NLP2020_CHIP_ID 0x0211 55 * The first nibble (bits 0 through 3) is changed with every revision 61 #define BCM_PHY_ID_MASK 0xfffff0f0 62 #define BCM8704_DEV_ID 0x206033 63 #define BCM5464R_PHY_ID 0x2060b1 64 #define BCM8706_DEV_ID 0x206035 [all …]
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/titanic_50/usr/src/cmd/bnu/ |
H A D | Uutry | 31 # -xN the debugging level for uucico (-x5 default) 40 if [ "`pwd`" != "/usr/lib/uucp" -a "$?" = 0 -a -x "./uucico" ]; then 50 X="-x5" 52 while [ $# -gt 0 ] 60 -?) echo "$0: unrecognized flag $1\nUSAGE: $0 [-r] [-xdebug_level] system";exit 1;; 67 echo "$0: system name required"
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/titanic_50/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/fw/ |
H A D | 57xx_fcoe_rfc_constants.h | 11 #define FC_TYPE_BLS 0x00 /* basic link service */ 12 #define FC_TYPE_ELS 0x01 /* extended link service */ 13 #define FC_TYPE_IP 0x05 /* IP over FC, RFC 4338 */ 14 #define FC_TYPE_FCP 0x08 /* SCSI FCP */ 15 #define FC_TYPE_CT 0x20 /* Fibre Channel Services (FC-CT) */ 16 #define FC_TYPE_ILS 0x22 /* internal link service */ 22 #define FC_RCTL_DDF 0x0 /* device data frames */ 23 #define FC_RCTL_ELS 0x2 /* extended link services */ 24 #define FC_RCTL_FC4_DATA 0x3 /* FC-4 Link Data */ 25 #define FC_RCTL_BLS 0x8 /* basic link services */ [all …]
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/titanic_50/usr/src/uts/common/sys/fibre-channel/fca/emlxs/ |
H A D | emlxs_dhchap.h | 47 #define ELX_DHCHAP 0x01 /* Only one currently supported */ 48 #define ELX_FCAP 0x02 49 #define ELX_FCPAP 0x03 50 #define ELX_KERBEROS 0x04 52 #define ELX_MD5 0x01 53 #define ELX_SHA1 0x02 55 #define ELX_GROUP_NULL 0x01 56 #define ELX_GROUP_1024 0x02 57 #define ELX_GROUP_1280 0x03 58 #define ELX_GROUP_1536 0x04 [all …]
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/titanic_50/usr/src/uts/common/sys/scsi/generic/ |
H A D | sff_frames.h | 61 SFF_GPIO_CFG = 0x00, 62 SFF_GPIO_RX = 0x01, 63 SFF_GPIO_RX_GP = 0x02, 64 SFF_GPIO_TX = 0x03, 65 SFF_GPIO_TX_GP = 0x04 72 SFF_GPIO_CFG_0 = 0x00, 73 SFF_GPIO_CFG_1 = 0x01 77 * SFF-8485 8.4.2.2 GPIO_CFG[0] register 129 SFF_DRIVE_ERR_DISABLE = 0x0, 130 SFF_DRIVE_ERR_ENABLE = 0x1, [all …]
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